From: Ken Wang
Signed-off-by: Ken Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5a4c074..ee565d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
The array[first] may be null when the fence has already been signaled.
BUG: SWDEV-136239
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/
Am 09.11.2017 um 00:54 schrieb Alex Deucher:
On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski wrote:
Hi,
Following series implements UVD support for SI in amdgpu driver. Code is based
on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
it requires tahiti uvd firmware
Just another alias for ttm_bo_unreserve.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +-
include/drm/ttm/ttm_bo_driver.h | 13 -
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c
b/drivers/gpu
Deleted BOs with the same reservation object can be reaped even if they
can't be reserved.
v2: rebase and we still need to remove/add the BO from/to the LRU.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 39 +++
1 file changed, 31 insertio
Consistently use the reservation object wrappers instead of accessing
the ww_mutex directly.
Additional to that use the reservation object wrappers directly instead of
calling __ttm_bo_reserve with fixed parameters.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 16 +++
Needed for the next patch and makes the code quite a bit easier to
understand.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c088703777e2..9
That's the only wrapper function missing and necessary to cleanup TTM.
Signed-off-by: Christian König
---
include/linux/reservation.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/include/linux/reservation.h b/include/linux/reservation.h
index 21fc84d82d41..02166e8
Instead of having a confusing wrapper or call the underlying ww_mutex
function directly.
Signed-off-by: Christian König
---
drivers/gpu/drm/qxl/qxl_release.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo.c | 13 +++--
drivers/gpu/drm/ttm/ttm_execbuf_util.c | 8
include/drm
Needed for the next patch.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 52
1 file changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 6f5d18366e6e..50a678b504
Am 09.11.2017 um 08:59 schrieb Emily Deng:
The array[first] may be null when the fence has already been signaled.
BUG: SWDEV-136239
Signed-off-by: Emily Deng
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +--
1 file changed, 5 insertions(+), 2 deletion
On 11/8/2017 11:39 PM, Mark Brown wrote:
On Wed, Nov 08, 2017 at 12:24:03PM -0500, Alex Deucher wrote:
regmap_read(regmap, RT5645_VENDOR_ID2, &val);
+ /*
+* Read after 400msec, as it is the interval required between
+* read and power On.
+*/
+ msleep(
Hi Monk.
I am interested on this. Currently when a "ring X stalled for more than N
sec" happens it usually goes into the gpu reset routine.
Does it always cause the vram to be lost ? Could you explain what happens
if the vram remains lost ?
I am asking this because I experienced some recurrent gp
I've accidentally pushed two incomplete WIP patches to the libdrm master
repository yesterday.
Just noticed the mistake and reverted the two.
Sorry for the noise,
Christian.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesk
On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski wrote:
> > Hi,
> >
> > Following series implements UVD support for SI in amdgpu driver. Code is
> > based
> > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To
Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski wrote:
Hi,
Following series implements UVD support for SI in amdgpu driver. Code is based
on CIK's UVD support in amdgpu and SI's UVD s
Reviewed-by: Nicolai Hähnle
On 08.11.2017 19:39, Tom St Denis wrote:
Signed-off-by: Tom St Denis
---
src/lib/wave_status.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/lib/wave_status.c b/src/lib/wave_status.c
index fe2add779fdd..7f0130bb9347 100644
--- a/src/lib/wave_status.
On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> > On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> > > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski
> > > wrote:
> > > > Hi,
> > > >
> > > > Following series imp
Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:
On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski wrote:
Hi,
Following
The logic was reversed when PRT support was added.
Signed-off-by: Tom St Denis
---
src/lib/read_vram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index b78d06194add..80f8e056258f 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/rea
On Thu, Nov 09, 2017 at 01:17:36PM +0100, Christian König wrote:
> Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:
> > On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> > > Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> > > > On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deuche
On Thu, Nov 09, 2017 at 09:42:57AM +0100, Christian König wrote:
> Am 09.11.2017 um 00:54 schrieb Alex Deucher:
> > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski
> > wrote:
> > > Hi,
> > >
> > > Following series implements UVD support for SI in amdgpu driver. Code is
> > > based
> > > on CIK'
Am 09.11.2017 um 15:37 schrieb Piotr Redlewski:
On Thu, Nov 09, 2017 at 09:42:57AM +0100, Christian König wrote:
Am 09.11.2017 um 00:54 schrieb Alex Deucher:
On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski wrote:
Hi,
Following series implements UVD support for SI in amdgpu driver. Code is ba
Not sure what that should originally been good for, but it doesn't seem
to make any sense any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/cik.c | 40 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 +++
drivers/gpu/drm/amd/amdgpu/d
Similar to the CPU address space the VA on Vega10 has a hole in it.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/
It's pointless to have the same value twice, just always use max_pfn.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 7 +++
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/
Even when it's a small handle it as 64bit value as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
On 09/11/17 03:49 PM, Christian König wrote:
> Similar to the CPU address space the VA on Vega10 has a hole in it.
[...]
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 4710e51099c2..81c34132fbd5 100644
> --- a/drivers/gpu/drm/amd/amdgpu
From: Colin Ian King
The index to vddci_buf is using profile->ucElbVDDC_Num rather
than profile->ucElbVDDCI_Num; this looks like a copy-n-paste
error from previous code for the vddc_buf array and I'm pretty
sure this is incorrect. Fix this by using the correct variable.
Detected by CoverityScan,
On Thu, Nov 9, 2017 at 3:03 AM, wrote:
> From: Ken Wang
>
> Signed-off-by: Ken Wang
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu
Am 09.11.2017 um 15:59 schrieb Michel Dänzer:
On 09/11/17 03:49 PM, Christian König wrote:
Similar to the CPU address space the VA on Vega10 has a hole in it.
[...]
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 4710e51099c2..81c34132fbd5
On Thu, Nov 9, 2017 at 9:49 AM, Christian König
wrote:
> Not sure what that should originally been good for, but it doesn't seem
> to make any sense any more.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/cik.c | 40
> +-
On Thu, Nov 9, 2017 at 9:49 AM, Christian König
wrote:
> It's pointless to have the same value twice, just always use max_pfn.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +-
> drivers/gpu/drm/amd/amdgpu/amdg
On 09/11/17 09:59 AM, Christian König wrote:
> Consistently use the reservation object wrappers instead of accessing
> the ww_mutex directly.
>
> Additional to that use the reservation object wrappers directly instead of
> calling __ttm_bo_reserve with fixed parameters.
>
> Signed-off-by: Christi
Am 09.11.2017 um 17:50 schrieb Michel Dänzer:
On 09/11/17 09:59 AM, Christian König wrote:
Consistently use the reservation object wrappers instead of accessing
the ww_mutex directly.
Additional to that use the reservation object wrappers directly instead of
calling __ttm_bo_reserve with fixed
From: Michel Dänzer
The atomic_check hook is expected to fail in some cases, e.g. if the
modeset operation requested by userspace cannot be performed, so it must
not spam dmesg on failure.
Fixes spurious
[drm:amdgpu_dm_atomic_check [amdgpu]] *ERROR* Atomic state validation failed
with error :
On Thu, Nov 9, 2017 at 6:35 AM, Colin King wrote:
> From: Colin Ian King
>
> The index to vddci_buf is using profile->ucElbVDDC_Num rather
> than profile->ucElbVDDCI_Num; this looks like a copy-n-paste
> error from previous code for the vddc_buf array and I'm pretty
> sure this is incorrect. Fix
On Thu, Nov 9, 2017 at 12:38 PM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> The atomic_check hook is expected to fail in some cases, e.g. if the
> modeset operation requested by userspace cannot be performed, so it must
> not spam dmesg on failure.
>
> Fixes spurious
>
> [drm:amdgpu_dm_atomi
On 09/11/17 09:59 AM, Christian König wrote:
> Deleted BOs with the same reservation object can be reaped even if they
> can't be reserved.
>
> v2: rebase and we still need to remove/add the BO from/to the LRU.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/ttm/ttm_bo.c | 39 +++
On Thu, Nov 9, 2017 at 4:35 AM, Julien Isorce wrote:
> Hi Monk.
>
> I am interested on this. Currently when a "ring X stalled for more than N
> sec" happens it usually goes into the gpu reset routine.
> Does it always cause the vram to be lost ? Could you explain what happens if
> the vram remains
On 2017-11-09 12:38 PM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> The atomic_check hook is expected to fail in some cases, e.g. if the
> modeset operation requested by userspace cannot be performed, so it must
> not spam dmesg on failure.
>
> Fixes spurious
>
> [drm:amdgpu_dm_atomic_check
From: Yue Hin Lau
dcn version of update_dchub now uses hubbub instead of hwseq
Change-Id: I6335897c721870cf023346dc52d65071a2f1cf8a
Signed-off-by: Yue Hin Lau
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +-
dr
From: Yongqiang Sun
Change-Id: I60d84f57d93870769fdb2d8f1e870121c2a28f15
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 19 ++-
.../gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2
From: Yue Hin Lau
no logic change
Change-Id: I31bdbba1abeb64d54e385456b58839160b1e188b
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
From: Charlene Liu
Change-Id: I98a09a622bbcf92e52377eb5eb14970bc604adc2
Signed-off-by: Charlene Liu
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/di
From: Yue Hin Lau
Change-Id: I01d8cc3095891bc44dcfb319729975b3dad6510e
Signed-off-by: Yue Hin Lau
Reviewed-by: Yuehin Lau
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 28 ++---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 29 +++
From: Eric Bernstein
Also move some register definitions to common DCN regs.
Change-Id: I6da468797abb0662e144aff073c62ab6a3ad430e
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 16
From: Tony Cheng
Change-Id: Iec51322a9e35f8ad8729168df7e6c88d42799e8c
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/d
From: Yue Hin Lau
Change-Id: Id7507b6af4ab877fc10c5549985ac2633fe3f124
Signed-off-by: Yue Hin Lau
Reviewed-by: Eric Bernstein
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 6 ++
dr
From: Tony Cheng
Change-Id: I8f2727ef40b40026483d2a0e465fb7f9b3916e31
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/d
From: Tony Cheng
Change-Id: I7c519d233b07bb45e27277aaa0ce046f54a94ef8
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/d
From: Dmytro Laktyushkin
This saves us about 5000 reg writes per full update. This translates to about
4 writes over the course of single eDP bootup.
Change-Id: If8e0c7bac744d8a3e2c56271c09453152025ccc8
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: Tony Cheng
Change-Id: I87463dfba34a246c9ec5f2a0cf417b9943683f7e
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/d
From: Dmytro Laktyushkin
When new coefficients match cached we would skip setting regamma mode
Also, when doing a stream update we would program regamma for all pipes,
even thos that are not yet powered on. This resulted in never setting
regamma since we would cache before the pipe is powered.
C
Previous code threw a warning about misleading indentation
Change-Id: I93e5998448e2c80d1b084231a3ef575bc1a0dfdd
Signed-off-by: Harry Wentland
Reviewed-by: Mikita Lipski
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
From: Eric Yang
When link training fail in MST case, we will divide by 0
when calculating avg_time_slots_per_mtp, so we cannot
proceed.
Change-Id: Iae7aef320deb3c204f3450544c36f89b075a5c21
Signed-off-by: Eric Yang
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c |
From: Dmytro Laktyushkin
Change-Id: Ida9244b5d9c44b8fc12c18a1bfb460e18778e04f
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
Change-Id: Ib7290f11372f258308a5e8be69f964e0407c54d6
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++--
.../amd/display/dc/dce110/dce110_
Trying to align with kernel coding style and make it a bit more
readable.
Change-Id: I7d4a06e221509a1b063c539223add2b73462a599
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 170 -
.../
From: Yongqiang Sun
Clear OPTC underflow status when init_hw.
Change-Id: I96953ee2d842a53ee343da88cffbef1eac2df95b
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++
drivers/gpu/drm/amd/disp
From: Eric Bernstein
Added a function to blank data using OPP DPG.
Clean up code to prepare for pseudocode review with HW.
Change-Id: Iac5e99e1eb72b8dd74c244e8d06d54bae9ab3ce2
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc
From: Yue Hin Lau
Change-Id: Id3ccff0209ae76330eb346c4ffd3aa3b6bf1909b
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
From: Eric Yang
Change-Id: Iebe803ec074af7648329af111217da2a50f8426c
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
drivers/gpu/drm/amd/display/dc
From: Roman Li
Replace ENABLE_FBC macro with config option CONFIG_DRM_AMD_DC_FBC
in dm. DC code has been already updated the same way.
Change-Id: I8c0e8deb6fe1387a7364822d12c2cc5beb888998
Signed-off-by: Roman Li
Reviewed-by: Shirish Shankarappa
Acked-by: Harry Wentland
---
drivers/gpu/drm/am
* Whole bunch of Raven (DCN) work
* Bunch of cleanups
Andrew Jiang (7):
drm/amd/display: Don't use dc_link in link_encoder
drm/amd/display: Report pitch_alignment for DCN
drm/amd/display: Loosen plane_info and scaling_info checks
drm/amd/display: Remove legacy unused workaround
drm/am
From: Yongqiang Sun
There are different code to disable front end, it is
difficult to debug and adding new process.
This refactor makes all disable front end call the same
functions.
Change-Id: Ia88b26851bcea426104a8dd9093b912d03424c9a
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked
From: Yongqiang Sun
Optimized front end initial sequence, reset MPC module
properly.
Change-Id: Id223308988505a15a9e0fc26f908beb1e42ed4a4
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 66
From: "Jerry (Fangzhi) Zuo"
It is to fix: MST display failed to resume from S3
Need to properly setup MST encoder cbs. Otherwise drm_device
encoder doesn't register its own cbs, leading to NULL
encoder->funcs in drm_atomic_helper_resume().
Change-Id: I2b2d1673d30e9a1765ad5bef97c98545b658b912
Si
From: "Jerry (Fangzhi) Zuo"
It is to fix: MST display failed to resume from S3
At the beginning of resume from S3, need to check if mgr->aux is
NULL. Fake MST encoder doesn't have real aux channel.
Change-Id: I15de6ab99da01841d62912dd98e6cc74d9100801
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed
From: "Leo (Sunpeng) Li"
This is a followup to the following revert:
Rex ZhuRevert "drm/amd/display: Match actual state during S3
resume."
Three things needed to be addressed:
1. Potential memory leak on dc_state creation in atomic_check during
s3 resume
2. Warnings are now s
From: Eric Bernstein
Change-Id: Ib79e69b0178219e02819a7b92cc1cb1bea9b5a68
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/i
From: Mikita Lipski
This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one
There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underf
From: Andrew Jiang
dc_link is at a higher level than link_encoder, and we only want
higher-level components to be able to access lower-level ones,
not the other way around.
Change-Id: I634b117b386938fb7ddba50c50484fadd54ad485
Signed-off-by: Andrew Jiang
Reviewed-by: Tony Cheng
Acked-by: Harry
From: Tony Cheng
Change-Id: If2b7804a5074077c3581f53db337768877fffc98
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/d
From: Dmytro Laktyushkin
Change-Id: I4c883547441b8db282efc6ced0930fca1cc1f043
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 9 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_h
From: Eric Yang
Temporary solution to fix gamma adjustment not
working.
Change-Id: I1884bcee28f7d71cbd5f6edd56423f01c32107b1
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +++-
1 file changed, 7
From: Charlene Liu
Change-Id: Ie8683cbe4791557054eba856aee6e06c948fc1f0
Signed-off-by: Charlene Liu
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 31 --
1 file changed, 29 insertions(+), 2 deletions(-)
diff --gi
From: Yue Hin Lau
following the naming convention with correct prefix
Change-Id: Ie4f2485f76ec9dc54a9aabea6f14a1119167d44e
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 16 +++
.../gpu/drm/amd/display/
From: Dmytro Laktyushkin
Change-Id: Ifde23126bc8528f42ad73fa19e6bf48d17a2233b
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gp
From: Bhawanpreet Lakha
This struct is not updated on page flip and causes vblank_mode
to not work as expected
Change-Id: I0e8684c5b67ec5670054f4bb849fa26bc60ed4b1
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c |
From: Yongqiang Sun
In case of update type is medium, optimize squence,
reduce programing time.
Change-Id: Ib1793408897b0c4d4a64434c239c3703d43e83d9
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 22 +
From: Eric Yang
output signal used to be a public member to be used by DM to override
the stream signal. Now since there is no longer separation between
public and private part of stream, they are combined. The overriding
was not working properly as well, which is addressed by this change
Change
From: "Leo (Sunpeng) Li"
This is a follow-up to the following change:
Yongqiang Sun: Program front end first when set mode.
Due to pipe-splitting features, how we handle stream enabling and
disabling needs to change.
In the case of pipe split disable, two planes need to be combined back
into t
Change-Id: Ibcc4e730884cc16688873115eac44d76957978f0
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 104 ++---
.../amd/display/dc/dce110/dce110_hw_sequencer.c|
Change-Id: I277078c8d6c547fb5a685845f6617bf9886c6fe4
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stre
Change-Id: I28eb763419eec834c591c03281abd22ad446b2e7
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/
From: Tony Cheng
plane update prior to stream enablement is there to recombine pipe
in case we need free pipe for new display. need to pass in new state
or we will just re-applyingwhat we already have
Change-Id: I688eced64db9ac785cd36a40603d158088f174f0
Signed-off-by: Tony Cheng
Reviewed-by: T
From: Andrew Jiang
Also initialize this to 64 for all ASICs.
Change-Id: Ia745d8d17e176ac2f65c6ac398d93bdc77fe75d6
Signed-off-by: Andrew Jiang
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
drivers/gpu/drm/amd/display/dc/dc.h
From: Andrew Jiang
This way, we can know exactly what triggered the update type we're
looking at, and we can simplify the logic for determining what exactly
needs to be updated in the future.
Also allow a dst rect size increase to go through a medium update,
since that does not require us to inc
From: Roman Li
also simplifying syntax and removing unused variable in
dce110_apply_ctx_for_surface()
Change-Id: I15c39de23afa05635d537ab2c5f8385342f75a64
Signed-off-by: Roman Li
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
From: Ken Chalmers
The ALLOW_SR registers might not always be available.
Change-Id: I715cffd3e56caee38ceed7af112182a7a51ce39a
Signed-off-by: Ken Chalmers
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 26 +++---
1 fil
From: Hersen Wu
SMU can future lower voltages in long idle case when all display is off.
If all display output is turned off via DPMS, send display_count = 0
after all output are turned off.
otherwise send display_count msg before turning on display to make sure
SMU exit S0i2 state. before is
From: Yongqiang Sun
Power on one plane after disable all the planes, for
a hw bug work around to resolve stutter efficiency issue.
Change-Id: Ifc696c800f9402afb9615a974657c8b06a94b334
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/displa
From: "Leo (Sunpeng) Li"
The fail goto is incorrect. It will incorrectly release the dc_states on
stream programming failure.
Change-Id: Ifefa4561266aaef10235e02dc687f5c0f637e6c1
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/
From: SivapiriyanKumarasamy
Change-Id: Ic42be4e0033db8d402f5688aef7c3cea6f7e0119
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/d
There's no need to have this as a vtable. The vtable was initially
used for stream_adjust_vmin_vmax but the condition checked here
(set_drr) is always true, hence we don't need to assign this
dynamically anymore.
Change-Id: I60e3c213b4566b3808b8feb001b93b74bcf7f17a
Signed-off-by: Harry Wentland
R
arr_points[1] and [2] were duplicated. Remove the extra
one. If we ever need more points we can add them but the
current state of affairs is confusing.
Change-Id: Ib72a1cb90940e9d52f241432c160f14393992523
Signed-off-by: Harry Wentland
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drive
From: "Leo (Sunpeng) Li"
on stream_for_cursor. Initialize to NULL.
Change-Id: Ic032bfe78b33e466e560d33488e0fd8df060f694
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Change-Id: Iff1b55b300bd6d874bd0dcbfe9fcf5d1ec43a7c9
Signed-off-by: Harry Wentland
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 33 +++---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 5 +-
.../amd/display/dc/dce110/dce110
From: Tony Cheng
Change-Id: I5fd90f7b53efd60dc2a0559edfcc90e9ab1bf5ff
Signed-off-by: Tony Cheng
Reviewed-by: Sun peng Li
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 32
1 file changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/di
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