Am 30.08.2017 um 23:08 schrieb Felix Kuehling:
set_pte_pde commands need 10 dwords.
But is only used when we write more than 3 consecutive entries, before
that we use write_pte which uses only 6 dw.
See amdgpu_vm_do_set_ptes() in amdgpu_vm.c
Regards,
Christian.
Signed-off-by: Felix Kuehl
Am 31.08.2017 um 01:26 schrieb Felix Kuehling:
One comment inline. With that fixed, this patch is Reviewed-by: Felix
Kuehling
On 2017-08-30 09:48 AM, Christian König wrote:
From: Roger He
This can improve performance for some cases.
v2 (chk): handle all sizes, simplify the patch quite a bi
From: Christian König
The IB allocation sizes where correct.
This reverts commit d1551e7c7211fa135c4d79f09e237f5f9779e421.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
Am 31.08.2017 um 04:00 schrieb zhoucm1:
On 2017年08月30日 21:48, Christian König wrote:
[SNIP]
+while (start != end) {
+/* This intentionally wraps around if no bit is set */
+frag = min(ffs(start), fls64(end - start)) - 1;
+if (frag >= max_frag)
+break;
Se
From: Roger He
This can improve performance for some cases.
v2 (chk): handle all sizes, simplify the patch quite a bit
v3 (chk): adjust dw estimation as well
v4 (chk): use single loop, make end mask 64bit
Signed-off-by: Roger He
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/a
On 2017年08月31日 17:44, Christian König wrote:
From: Roger He
This can improve performance for some cases.
v2 (chk): handle all sizes, simplify the patch quite a bit
v3 (chk): adjust dw estimation as well
v4 (chk): use single loop, make end mask 64bit
Signed-off-by: Roger He
Signed-off-by: C
From: Michel Dänzer
xserver 1.13.0 was released on September 6th, 2012, almost 5 years ago.
This allows cleaning up a bunch of backwards compatibility code.
(Ported from radeon commit 5cdd334b3402c2431deb3a87a8d04ef590da53ee)
Signed-off-by: Michel Dänzer
---
configure.ac | 8
From: Christian König
We need to refer to the parent instead of the root BO for multi
level page tables on Vega10. Also don't set the PDE_PTE bit.
v2: Don't set the PDE_PTE bit either.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
1 file changed, 2 insert
Reviewed-and-Tested-by: Roger He
Thanks
Roger(Hongbo.He)
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Thursday, August 31, 2017 7:58 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: fix new PD update
Am 31.08.2017 um 00:50 schrieb Felix Kuehling:
Reviewed-by: Felix Kuehling
Some more thoughts inline, but nothing that should be addressed in this
change.
Regards,
Felix
On 2017-08-30 11:00 AM, Christian König wrote:
From: Christian König
Per VM BOs are handled like VM PDs and PTs. The
Am 31.08.2017 um 00:55 schrieb Felix Kuehling:
On 2017-08-30 11:00 AM, Christian König wrote:
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -136,7 +136,8 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device
*dev,
{
struct am
Working on a series of tidy up patches for gfx_v9 and found this block
in gfx_v9_0_sw_init().
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
ring->ring_obj = NULL;
sprintf(ring->name, "gfx");
Won't that make
> > Just thinking out loud: Per VM BOs don't need to be cleared because they
> > have separate lists for evicted and moved (but valid) BOs.
>
> Actually the reason is that we know they are reserved together with the
> page directory.
I mentioned separate lists because that allows us to distinguish
Am 31.08.2017 um 15:20 schrieb Kuehling, Felix:
Just thinking out loud: Per VM BOs don't need to be cleared because they
have separate lists for evicted and moved (but valid) BOs.
Actually the reason is that we know they are reserved together with the
page directory.
I mentioned separate lists
>>> +frag_end = end & ~((1 << max_frag) - 1);
>> You need a cast to uint64_t to make sure your mask is big enough and
>> doesn't wipe out the high address bits:
>>
>> frag_end = end & ~(uint64_t)((1 << max_frag) - 1)
>
> Good point. Using "frag_end = end & ~((1ULL << max_frag) - 1)
Yeah, I realized this later last night. I'm going to do some more debugging to
track down the real problem today.
For now, this seems to have moved around IB allocations enough to hide the
problem so our merge today seems to have passed PSDB. But like I said, at best
I've hidden the problem, no
Reviewed-by: Felix Kuehling
Sorry, I didn't think this one through. I'll keep looking for the real problem.
From: amd-gfx on behalf of Christian
König
Sent: Thursday, August 31, 2017 3:45:48 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdg
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Thursday, August 31, 2017 5:57 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-amdgpu] Require xserver >= 1.13
>
> From: Michel Dänzer
>
> xserver
Am 31.08.2017 um 15:42 schrieb Kuehling, Felix:
Reviewed-by: Felix Kuehling
Thanks.
Sorry, I didn't think this one through. I'll keep looking for the real problem.
Is it possible that you merged my earlier patch to handle all fragment
sizes?
Cause earlier versions had exactly that probl
Am 31.08.2017 um 15:59 schrieb Jerome Glisse:
[Adding Intel folks as they might be interested in this discussion]
On Wed, Aug 30, 2017 at 05:51:52PM -0400, Felix Kuehling wrote:
Hi Jérôme,
I have some questions about the potential range-start-end race you
mentioned.
On 2017-08-29 07:54 PM, Jé
From: Christian König
David please provide an open source user, otherwise
we need to remove this again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 142 +
1 file changed, 1 insertion(+), 141 deletions(-)
diff --git a/drivers/gpu/
On Fri, Aug 18, 2017 at 02:10:27PM -0400, Alex Deucher wrote:
> From: Vijendar Mukunda
>
> For Stoney platform, Memory gating is disabled.i.e SRAM Banks
> won't be turned off. By Default, SRAM Bank state set to ON.
> Added condition checks to skip SRAM Bank state set logic for
> Stoney platform.
On Wed, Aug 30, 2017 at 09:40:07PM +, Deucher, Alexander wrote:
Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns. Doing this makes your messages much
easier to read and reply to.
> I sent one patch in the v2 patch set that had already
On Fri, Aug 18, 2017 at 02:10:30PM -0400, Alex Deucher wrote:
> +++ b/sound/soc/amd/Kconfig
> @@ -2,3 +2,10 @@ config SND_SOC_AMD_ACP
> tristate "AMD Audio Coprocessor support"
> help
>This option enables ACP DMA support on AMD platform.
> +config SND_SOC_AMD_CZ_RT5645_MACH
> +
On Fri, Aug 18, 2017 at 02:10:29PM -0400, Alex Deucher wrote:
> +#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
> +#define ST_CAPTURE_MAX_PERIOD_SIZE 8192
> +#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE *
> PLAYBACK_MAX_NUM_PERIODS)
These defines will go wrong if the capture size is changed ind
On Fri, Aug 18, 2017 at 02:10:28PM -0400, Alex Deucher wrote:
> From: Vijendar Mukunda
>
> Added DMA driver changes for Stoney platform.
> Below are the key differences between Stoney and CZ
Acked-by: Mark Brown
signature.asc
Description: PGP signature
[Adding Intel folks as they might be interested in this discussion]
On Wed, Aug 30, 2017 at 05:51:52PM -0400, Felix Kuehling wrote:
> Hi Jérôme,
>
> I have some questions about the potential range-start-end race you
> mentioned.
>
> On 2017-08-29 07:54 PM, Jérôme Glisse wrote:
> > Note that a lo
On 2017-08-31 09:59 AM, Christian König wrote:
> Am 31.08.2017 um 15:42 schrieb Kuehling, Felix:
>> Reviewed-by: Felix Kuehling
>
> Thanks.
>
>> Sorry, I didn't think this one through. I'll keep looking for the
>> real problem.
>
> Is it possible that you merged my earlier patch to handle all frag
Am 31.08.2017 um 17:50 schrieb Felix Kuehling:
On 2017-08-31 09:59 AM, Christian König wrote:
Am 31.08.2017 um 15:42 schrieb Kuehling, Felix:
Reviewed-by: Felix Kuehling
Thanks.
Sorry, I didn't think this one through. I'll keep looking for the
real problem.
Is it possible that you merged m
Reviewed-by: Felix Kuehling
This looks very elegant now. :)
On 2017-08-31 05:44 AM, Christian König wrote:
> From: Roger He
>
> This can improve performance for some cases.
>
> v2 (chk): handle all sizes, simplify the patch quite a bit
> v3 (chk): adjust dw estimation as well
> v4 (chk): use si
No real functional changes just code style improvements and
cleanups.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 01f8b1e79540..c0db82a1ad61 100644
--- a/drivers/gpu/drm/a
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 96 +++
1 file changed, 64 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae393705decb..a3986e688757 100644
--
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a3986e688757..99cd10eceea9 100644
--- a/driver
Make it consistent in style with the other CG/PG enable functions...
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
ind
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 99cd10eceea9..53ef3769df0c 100644
--- a/drivers/gpu/drm/amd
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 807830a38835..20d4097343bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f92299c71f46..807830a38835 100644
--- a/drivers/gpu/drm/amd/amdgpu/
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d235dc23a6bf..79c5df55b616 100644
--- a/drivers/gpu/drm/a
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 53ef3769df0c..d235dc23a6bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gf
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 79c5df55b616..01f8b1e79540 100644
--- a/drivers/gpu/drm/a
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 20d4097343bb..c45c69c4673b 100644
--- a/drivers/gpu/drm/amd/amdgpu/
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bf4245a435ae..9445a8fd13ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9445a8fd13ba..00f082b0838f 100644
--- a/drivers/gpu/drm/amd/amdgpu/g
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c45c69c4673b..bf4245a435ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/g
On Thu, Aug 31, 2017 at 12:06 PM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++--
> 1 file changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0
On Thu, Aug 31, 2017 at 12:06 PM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis
One comment on patch 3. The rest are:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd
On 31/08/17 12:27 PM, Alex Deucher wrote:
On Thu, Aug 31, 2017 at 12:06 PM, Tom St Denis wrote:
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/d
From: Duke Du
Signed-off-by: Duke Du
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +
drivers/gpu/drm/amd/display/dc/dc.h| 2 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 87 ++-
.../gpu/drm/amd/displ
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/d
From: Corbin McElhanney
This comment explains a previous change that adds some complexity
to the context free in dc:
commit 9ad58779a895 ("drm/amd/display: Fix accessing freed memory")
Signed-off-by: Corbin McElhanney
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/
From: Zeyu Fan
Signed-off-by: Zeyu Fan
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 69
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 420 -
drivers/gpu/drm/amd/display/dc/dc.h| 1
From: Roman Li
Removed FBC disable from dc_enable_stereo().
It should be implemented in stereo_setup callback, which is not
implemented yet. Otherwise it always disable FBC regardless
if stereo supported or not.
Signed-off-by: Roman Li
Reviewed-by: Bhawanpreet Lakha
Acked-by: Harry Wentland
-
A long list of changes all at once again, this time, since
we've had a couple regressions to iron out.
* Build state per streams and planes to follow model
of other atomic drivers
* Rename context to state to avoid confusion
* Flatten core_dc object
* Remove bunch of unneeded code
* Rewor
From: Andrey Grodzovsky
Until now new context would start as empty, then populated
with exsisting pipes + new. Now we start with duplication
of existing context and then add/delete from the context
pipes as needed.
This allows to do a per stream resource
population, start discarding dc_validatio
From: Charlene Liu
also pass-in correct dispclk tor DMCU
Signed-off-by: Charlene Liu
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 12 +---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 22 ++
...
From: Jerry Zuo
Current ref_count inc/dec is not guarded by locks which leads to
a raced condition where two threads try to access the variable
at the same time. In this case, both might act on the same cached
value and inc/dec from the same value, rather than inc/dec by 2.
Signed-off-by: Jerry
From: Roman Li
Added missing reg shift/masks to soc base
Signed-off-by: Roman Li
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
b/drivers/gpu/drm/amd/
See
https://lists.freedesktop.org/archives/dri-devel/2017-August/149938.html
Signed-off-by: Harry Wentland
Reviewed-by: Jordan Lazare
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dm_services.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/d
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 5 -
3 files changed, 7 in
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 69f67f6e27b1..54e37b10ffbf
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/disp
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 23 ++
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +-
2 files changed, 24 insertions(+), 1 deletion(-)
di
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 662 --
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 34
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 41 +++---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 25 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_c
From: Tony Cheng
set dcfclk and fclk req with pp_smu_display_requirement_rv
Change-Id: Ifb26473798cb6d7b79dd831900dfc3abb939f4eb
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 26 +-
d
Change-Id: I967334d365b5b7780af8e63de0196cf4ce9903e3
Signed-off-by: Harry Wentland
Reviewed-by: Roman Li
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_se
From: Corbin McElhanney
Signed-off-by: Corbin McElhanney
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 33 +
.../amd/display/dc/dcn10/dcn10_timing_generator.c | 42 ++
.../amd/display/dc/dcn10/dcn
From: Wenjing Liu
[Description]
Audio should be attached to the same pipe once it is attached.
We will not remove audio endpoint in disable stream.
We will reeanble the audio after automated link training test
Signed-off-by: Wenjing Liu
Reviewed-by: Tony Cheng
Reviewed-by: Charlene Liu
Acked-
From: Eric Bernstein
Change-Id: I1efc6d2cda212008597784be9bf4c11db48ee180
Signed-off-by: Eric Bernstein
Signed-off-by: Tony Cheng
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 101 ++---
1 file changed, 29 in
From: Andrey Grodzovsky
Starting with 4.12 kernel DRM provides page flip flags so we
don't need to have our own copy.
Change-Id: I15d8db215001f887c47d16be82df04216f9265c3
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++-
Signed-off-by: Harry Wentland
Reviewed-by: Andrey Grodzovsky
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc
From: Bhawanpreet Lakha
Change-Id: I1735203833573473200e19bf0324aecd92663535
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 145 --
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 73 ---
dri
From: Tony Cheng
Change-Id: I46ef2f3c129dd712b9e19f4c459d4bb5a40569c5
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
2 files changed, 4 insertions(+), 1 deletion(
From: Tony Cheng
new per SoC interface instead legacy interface with lots of un-used
field that only cause confusion
model pp_smu like one of our HW objects with func_ptr interface
to call into it. struct pp_smu as handle to call pp/smu
Signed-off-by: Tony Cheng
Reviewed-by: Jun Lei
Acked-by
From: Dmytro Laktyushkin
This should be handled by mi and mpc only
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c| 2 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++
dr
From: Bhawanpreet Lakha
-Change bw_calcs_dceip into pointer
-Change bw_calcs_vbios into pointer
This is needed for flattening of core_dc into dc, as without this the
diags build fails
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Wenjing Liu
Signed-off-by: Wenjing Liu
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Roman Li
1.Fixing error message:
"wait counter exceeded, changes to HW not applied"
2. Added "FBC status changed to 0/1" logs
Signed-off-by: Roman Li
Reviewed-by: Bhawanpreet Lakha
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 8 +++-
1 fi
From: Roman Li
- Fixing compilation with ENABLE_FBC flag
which was broken after flattening core_dc to dc
Signed-off-by: Roman Li
Reviewed-by: Jerry Zuo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/d
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
From: Bhawanpreet Lakha
-Change dcn_ip into pointer
-Change dcn_soc into pointer
This is needed for flattening of core_dc into dc, as without
this the diags build fails
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 553 +
From: Wenjing Liu
[Description]
Link training is not retried in automated link training request.
In case link training is occasionally failing, there is not way to retry
so the requested lane settings will not set.
Change-Id: I46fbdcf9d115bb5d8a841134e5db2c95ef81ee3f
Signed-off-by: Wenjing Liu
From: Charlene Liu
Change-Id: I902f693c9501737c8611c641f589b23fdfe5da50
Signed-off-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 4
drivers/gpu/d
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 3 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 650 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 5
From: Wenjing Liu
Change-Id: Ifa864d3788ae34a6dfa315bd4148f5d5c4ae0c5a
Signed-off-by: Wenjing Liu
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_
From: Yue Hin Lau
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 52 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 95 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.
From: Dmytro Laktyushkin
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 6 +++---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4
2 files changed, 7 insertions(+), 3 deletions(-)
diff -
From: Jerry Zuo
1. Change 100104: Move verify link cap after read edid causes MST
link_cap struct not being set. It leads to zero denominator
pbn_per_slot value, leading to the crash at
dal_fixed31_32_div(). Skip MST link training for now and will
need to add MST specific link traning
From: Yongqiang Sun
Change-Id: I69bcb30ffb1ec1409d8e61adc009b9c87a7ccc30
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/d
From: Yongqiang Sun
Change-Id: I1a7819cdb737b9cdab31479c91a389119f23b296
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
2 files
From: Yongqiang Sun
Change-Id: Iedc229c5bb753ad64819ffb1bbea1909764e46db
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 10 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator
From: Yue Hin Lau
Change-Id: Ifeca77690784f197273f2d41e67b331ad9dfe674
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 420 --
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 628 +---
From: Wenjing Liu
[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.
Change-Id: I057bab303ee15ceccb458beeb5a61aab9208
From: Yue Hin Lau
Change-Id: Ic3096918ef31786ff523ed1487bde5afb9382f91
Signed-off-by: Yue Hin Lau
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 20 ---
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 20 ---
.../
From: Jerry Zuo
The fix is for the scenario: MST+SST chain together, and hook up
to the card.
Regression: Per stream validate_context build v2
Before dc_add_stream_to_ctx(), need to update/reset
stream signal type to SIGNAL_TYPE_DISPLAY_PORT_MST. Otherwise,
downstream device cannot be added to c
From: Charlene Liu
Change-Id: Id83238a2f1b7cc66bdf7a9a02fc630f8805fdd17
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1
From: Yongqiang Sun
Change-Id: Ife3ff042c9f70a6e8c08f0e5a395117de04eed14
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 10 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator
1 - 100 of 138 matches
Mail list logo