Signed-off-by: Huang Rui
Cc: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 5bed483..60d0455 100644
--- a/drivers/gpu/drm/amd/amd
Am 26.06.2017 um 08:12 schrieb Flora Cui:
keep cu_ao_mask unchanged for backward compatibility.
Change-Id: I9f497aadd309977468e246fea333b392c0150276
Signed-off-by: Flora Cui
---
This patch should be landed after the kmd patch upsteam. right?
In general yes, but this patch is a NAK as well.
Am 26.06.2017 um 09:03 schrieb Huang Rui:
Signed-off-by: Huang Rui
Cc: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 5bed483
caused by not program dynamic_cu_mask_addr in the KIQ MQD.
v2: create struct vi_mqd_allocation in FB which will contain
1. PM4 MQD structure.
2. Write Pointer Poll Memory.
3. Read Pointer Report Memory
4. Dynamic CU Mask.
5. Dynamic RB Mask.
Change-Id: I22c840f1bf8d365f7df33a27d6b11e1aea8f2958
Si
On 23/06/17 07:49 PM, Marek Olšák wrote:
> On Fri, Jun 23, 2017 at 11:27 AM, Christian König
> wrote:
>> Am 23.06.2017 um 11:08 schrieb zhoucm1:
>>> On 2017年06月23日 17:01, zhoucm1 wrote:
On 2017年06月23日 16:25, Christian König wrote:
> Am 23.06.2017 um 09:09 schrieb zhoucm1:
>> On 2017年0
On 2017年06月26日 03:48, Dave Airlie wrote:
Do you not use bo list at all in mesa? radv as well?
Currently radv is creating a bo list per command submission. radv does
not use an offload thread to do command submission, as it seems pretty
un-vulkan to use a thread for the queue submission thread
On Thu, Jun 22, 2017 at 08:06:25AM +0200, Peter Rosin wrote:
> drm_fb_helper_save_lut_atomic is redundant since the .gamma_store is
> now always kept up to date by drm_fb_helper_setcmap.
>
> Signed-off-by: Peter Rosin
Also note that this is for kgdb support only and so likely very buggy
(since n
On Thu, Jun 22, 2017 at 08:06:26AM +0200, Peter Rosin wrote:
> This makes the redundant fb helpers .load_lut, .gamma_set and .gamma_get
> totally obsolete.
>
> Signed-off-by: Peter Rosin
> ---
> drivers/gpu/drm/drm_fb_helper.c | 154
>
> 1 file changed,
On 25/06/17 03:00 AM, Christian König wrote:
> Am 23.06.2017 um 19:39 schrieb John Brooks:
>> When the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag is given by
>> userspace,
>> it should only be treated as a hint to initially place a BO somewhere CPU
>> accessible, rather than having a permanent effe
On Thu, Jun 22, 2017 at 08:06:24AM +0200, Peter Rosin wrote:
> I think the gamma_store can end up invalid on error. But the way I read
> it, that can happen in drm_mode_gamma_set_ioctl as well, so why should
> this pesky legacy fbdev stuff be any better?
>
> Signed-off-by: Peter Rosin
> ---
> dr
On Thu, Jun 22, 2017 at 12:22:10PM +0200, Peter Rosin wrote:
> This makes the redundant fb helpers .load_lut, .gamma_set and .gamma_get
> totally obsolete.
>
> Signed-off-by: Peter Rosin
> ---
> drivers/gpu/drm/drm_fb_helper.c | 151
> +---
> 1 file changed,
On Thu, Jun 22, 2017 at 08:06:23AM +0200, Peter Rosin wrote:
> Hi!
>
> While trying to get CLUT support for the atmel_hlcdc driver, and
> specifically for the emulated fbdev interface, I received some
> push-back that my feeble in-driver attempts should be solved
> by the core. This is my attempt
On 24/06/17 02:39 AM, John Brooks wrote:
> There is no need for page faults to force BOs into visible VRAM if it's
> full, and the time it takes to do so is great enough to cause noticeable
> stuttering. Add GTT as a possible placement so that if visible VRAM is
> full, page faults move BOs to GTT
On 24/06/17 02:39 AM, John Brooks wrote:
> The BO move throttling code is designed to allow VRAM to fill quickly if it
> is relatively empty. However, this does not take into account situations
> where the visible VRAM is smaller than total VRAM, and total VRAM may not
> be close to full but the vi
On 24/06/17 02:39 AM, John Brooks wrote:
> Allow specifying a limit on visible VRAM via a module parameter. This is
> helpful for testing performance under visible VRAM pressure.
>
> Signed-off-by: John Brooks
Reviewed-by: Michel Dänzer
--
Earthling Michel Dänzer |
Hi Harish,
have you committed that to amd-staging-4.11? If not can you do so today?
I'm still getting compiler warnings from the VM code.
Regards,
Christian.
Am 23.06.2017 um 19:54 schrieb Felix Kuehling:
Sorry for the delay.
The series is Reviewed-by: Felix Kuehling .
Regards,
Felix
On
Am 23.06.2017 um 19:39 schrieb John Brooks:
Allow specifying a limit on visible VRAM via a module parameter. This is
helpful for testing performance under visible VRAM pressure.
Signed-off-by: John Brooks
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dr
From: Michel Dänzer
The declaration has been moved there from dri.h.
Signed-off-by: Michel Dänzer
---
src/radeon_probe.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index aaace2b5f..19295f00c 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_
On Mon, Jun 26, 2017 at 03:18:52PM +0800, Christian König wrote:
> Am 26.06.2017 um 09:03 schrieb Huang Rui:
> > Signed-off-by: Huang Rui
> > Cc: Xiaojie Yuan
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/driv
Am 26.06.2017 um 12:53 schrieb Huang Rui:
On Mon, Jun 26, 2017 at 03:18:52PM +0800, Christian König wrote:
Am 26.06.2017 um 09:03 schrieb Huang Rui:
Signed-off-by: Huang Rui
Cc: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Signed-off-by: Huang Rui
---
V1 -> V2:
- Add READ_ONCE to avoid complier might cause to read as previous fence value.
I will refine fence checking with fence interface at amdgpu_fence.c after S3
stress issue completed as Christian's suggestion.
Thanks,
Ray
---
drivers/gpu/drm/amd/amdgpu/amdgp
Am 26.06.2017 um 14:18 schrieb Huang Rui:
Signed-off-by: Huang Rui
Acked-by: Christian König .
---
V1 -> V2:
- Add READ_ONCE to avoid complier might cause to read as previous fence value.
I will refine fence checking with fence interface at amdgpu_fence.c after S3
stress issue completed as
Am 23.06.2017 um 19:05 schrieb Alex Deucher:
On Fri, Jun 23, 2017 at 12:43 PM, Christian König
wrote:
Am 23.06.2017 um 18:34 schrieb Alex Deucher:
From: Vijendar Mukunda
asic_type information is passed to ACP DMA Driver as platform data.
We need this to determine whether the asic is Carrizo
Sorry for the delay, back from a rather long sick leave today and trying
to catch up with my work.
Quick ping on the query above. The query can be summarized as: which
ioctl interface do we prefer for the override?
* AMDGPU_SCHED_OP_PROCESS_PRIORITY_GET/PUT - refcounted override
or
* AM
From: Christian König
Stop spreading the code over all GMC generations.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 20
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c| 10 +-
drivers/gpu/
From: Christian König
Limit the size of the GART table for the system domain.
This saves us a bunch of visible VRAM, but also limitates the maximum BO size
we can swap out.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgp
From: Christian König
Otherwise we trigger a bunch of WARN_ONs when this is called.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/d
> -Original Message-
> From: Huang Rui [mailto:ray.hu...@amd.com]
> Sent: Monday, June 26, 2017 8:18 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Qiao, Joe(Markham); Jiang, Sonny; Huan, Alvin; Huang, Ray
> Subject: [PATCH v2] drm/amdgpu: fix
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Monday, June 26, 2017 3:26 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: fix vulkan test performance drop and hang
> on VI
>
> caused by
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Monday, June 26, 2017 5:59 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-ati] Include xf86Pci.h for DRICreatePCIBusID with
> xserver Git master
>
>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Monday, June 26, 2017 9:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: j...@fastquake.com; Kuehling, Felix
> Subject: [PATCH 1/3] drm/amdgpu: cleanup initializing gtt_
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Monday, June 26, 2017 9:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: j...@fastquake.com; Kuehling, Felix
> Subject: [PATCH 2/3] drm/amdgpu: fix amdgpu_debugfs_gem_bo
> -Original Message-
> From: Panariti, David
> Sent: Monday, June 26, 2017 12:06 PM
> To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 3/3] drm/amdgpu: Add kernel parameter to control use
> of ECC/EDC.
>
> >> > I'd suggest setting amdgpu_ecc_flags to AMD_ECC_SUPP
On 2017-06-26 09:32 AM, Christian König wrote:
Sorry for the delay, back from a rather long sick leave today and trying
to catch up with my work.
Don't worry too much. Get well soon!
Quick ping on the query above. The query can be summarized as: which
ioctl interface do we prefer for the
>> > I'd suggest setting amdgpu_ecc_flags to AMD_ECC_SUPPORT_BEST by
>> > default. That can be our asic specific default setting. In the
>> > case of CZ, that will be disabled until we decide to enable EDC by default.
>> [davep] I'm confused. ECC...BEST will cause EDC to be enabled.
>> I used
Hi,
I have not checked the background of this discussion very closely yet. And you
might have known the following.
Customers may not want the default setting to change meaning. This is like an
API.
Example: The application and its environment is already set up and tested. Then
if customer upda
Sorry for the delay. I have rebased and pushed my changes.
Best Regards,
Harish
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian König
Sent: Monday, June 26, 2017 5:55 AM
To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org;
Kasivisw
On 2017-06-20 01:57 PM, Andrey Grodzovsky wrote:
> Problem : While running IGT kms_atomic_transition test suite i encountered
> a hang in drmHandleEvent immediately following an atomic_commit.
> After dumping the atomic state I relized that in this case there was
> not even one CRTC attached to th
Agreed... one person's "best" is another person's "OMG I didn't want that". IMO
we should have bits correspond to specific options as much as possible, modulo
HW capabilities.
>-Original Message-
>From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Xie, AlexBin
>Se
>
> I'm traveling and cannot make progress this week. The merge window is
> also real close so this series will therefore probably miss it unless
> something unexpected happens...
Don't worry you missed the merge window for drm already, we don't merge
things after -rc6. Please remember the Linus m
I'm wondering what makes this possible. Let me quote the last discussion
we had about GART:
> On 17-04-04 06:26 PM, Felix Kuehling wrote:
>> Even with GART address space being allocated on demand, it still seems
>> to be limiting the maximum available system memory that can be allocated
>> from TT
Add an initial framework for changing the HW priorities of rings. The
framework allows requesting priority changes for the lifetime of an
amdgpu_job. After the job completes the priority will decay to the next
lowest priority for which a request is still valid.
A new ring function set_priority() c
This is useful for changing an entity's priority at runtime.
v2: don't modify the order of amd_sched_entity members
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 26 +++---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 3 +++
2 files
Returning invalid priorities as _NORMAL is a backwards compatibility
quirk of amdgpu_ctx_ioctl(). Move this detail one layer up where it
belongs.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 +---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 3 ++-
Use _INVALID to identify bad parameters and _UNSET to represent the
lack of interest in a specific value.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 ++
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 3 ++-
include/uapi/drm/amdgpu_drm.h
Introduce amdgpu_ctx_priority_override(). A mechanism to override a
context's priority.
An override can be terminated by setting the override to
AMD_SCHED_PRIORITY_UNSET.
v2: change refcounted interface for a direct set
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
The AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE ioctls are used to set the
priority of a different process in the current system.
When a request is dropped, the process's contexts will be
restored to the priority specified at context creation time.
A request can be dropped by setting the override p
Add a new context creation parameter to express a global context priority.
The priority ranking in descending order is as follows:
* AMDGPU_CTX_PRIORITY_HIGH_HW
* AMDGPU_CTX_PRIORITY_HIGH_SW
* AMDGPU_CTX_PRIORITY_NORMAL
* AMDGPU_CTX_PRIORITY_LOW_SW
* AMDGPU_CTX_PRIORITY_LOW_HW
The driver wil
Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over
other queues on the same pipe. Multiple queues on a pipe are timesliced
so this gives us full precedence over other queues.
Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the
wave as follows:
0x2: CS_
Updated with Christian's request to simplify the process priority
override interface.
Series available in the wip-process-priorities-v2 branch of:
git://people.freedesktop.org/~lostgoat/linux
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https
From: Charlene Liu
Change-Id: Ib1f8c3b34b0144edade8331b0c2782c1df793020
Signed-off-by: Charlene Liu
Reviewed-by: Aric Cyr
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/d
If we don't have a surface in dc_commit_streams scl_data won't get
populated in resource_build_scaling_params_for_context. In this case we
shouldn't attempt to program the scaler.
Change-Id: Ib901a062e4b0b897629ee1a1eaf2e7e1a5334cbf
Signed-off-by: Harry Wentland
Reviewed-by: Dmytro Laktyushkin
A
From: "Leo (Sunpeng) Li"
IGT currently does not properly commit changes on planes with multiple
possible CRTC's. Set one valid CRTC for each plane for now, plus one
underlay plane on Carizzo and Stoney that is valid for all CRTCs.
Change-Id: Ifcc37754a6e93e6fd9693d028354fa678c3a5d72
Signed-off-b
From: Dmytro Laktyushkin
The compiler was warning about conditions that will never evaluate
to true. The problem was that the VBA translater didn't translate
the conditions correctly.
Change-Id: Ie5b3e674460bdd46e9854480c2fa5ae732427dea
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Harry Wentl
* Global lock to properly lock DC commits
* Fix single MST support (atomic_get_property missing)
* IGT fix for multi-plane configurations
* Updated DCN bandwidth formula
* Bunch of minor fixes
Andrey Grodzovsky (5):
drm/amd/display: MST atomic_get_property missing.
drm/amd/display: Add gl
From: Dmytro Laktyushkin
Change-Id: I5c49ef7cb779c1238796a2d071432255653afa64
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drive
From: Andrey Grodzovsky
Switch to wait_for_completion_interruptible_timeout wait
since the lock is called from IOCTL context and can be
interrupted by a signal.
Global lock function might return EDEADLK or EINTR which
is not an error and just singals to user mode to restart
the call.
Change-Id:
From: Andrey Grodzovsky
Due to using dc_commit_surface_to_stream instead of build
stream and surface updates any surface commit today is
evlauted to full. Until we fix this and can corretly
evluate type of surface update, anything which is not page
flip or cursor update will be treted as full upd
From: Andrey Grodzovsky
Fix typos.
Change-Id: Ib152dffe835dd7b11ad2fca20d467dd36edca70d
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Roman Li
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
dif
From: Andrey Grodzovsky
Missing function implementation was leading to EINVAL
in UMD thus not adding MST connector to X topology
and hence not getting set mode for it.
Change-Id: I913039185c3e1ab13605ef394a5e7c550025db4a
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry Wentland
---
drivers
From: Andrey Grodzovsky
Change-Id: Ifc5e7c383c9be8fdda0989b9a91f8602487ccbb5
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry Wentland
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 66 --
1 file changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/
From: Yongqiang Sun
Change-Id: I7d3c8677e236003386ddc7dfd3511b6a13a89829
Signed-off-by: Yongqiang Sun
Reviewed-by: Hersen Wu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/a
From: Dmytro Laktyushkin
Change-Id: I4bf181d16258f8fa871ebd4fa41b2140f9bf0c60
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 11 ---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
2
> -Original Message-
> From: Bridgman, John
> Sent: Monday, June 26, 2017 3:12 PM
> To: Xie, AlexBin ; Panariti, David
> ; Deucher, Alexander
> ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 3/3] drm/amdgpu: Add kernel parameter to control use
> of ECC/EDC.
>
> Agreed... one perso
From: Dave Airlie
This adds the corresponding code for libdrm to use the new
kernel interfaces for semaphores.
This will be used by radv to implement shared semaphores.
TODO: Version checks.
Signed-off-by: Dave Airlie
---
amdgpu/amdgpu.h | 28 +
amdgpu/amdgpu_cs.c | 1
On Mon, Jun 26, 2017 at 06:44:30PM +0900, Michel Dänzer wrote:
> On 24/06/17 02:39 AM, John Brooks wrote:
> > The BO move throttling code is designed to allow VRAM to fill quickly if it
> > is relatively empty. However, this does not take into account situations
> > where the visible VRAM is smalle
On Mon, Jun 26, 2017 at 11:27 AM, Michel Dänzer wrote:
> On 25/06/17 03:00 AM, Christian König wrote:
>> Am 23.06.2017 um 19:39 schrieb John Brooks:
>>> When the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag is given by
>>> userspace,
>>> it should only be treated as a hint to initially place a BO so
On Mon, Jun 26, 2017 at 03:39:57PM +0200, Christian König wrote:
> From: Christian König
>
> Limit the size of the GART table for the system domain.
>
> This saves us a bunch of visible VRAM, but also limitates the maximum BO size
> we can swap out.
>
> Signed-off-by: Christian König
Hmm.
O
On 2017-06-26 11:35, Daniel Vetter wrote:
> On Thu, Jun 22, 2017 at 08:06:23AM +0200, Peter Rosin wrote:
>> Hi!
>>
>> While trying to get CLUT support for the atmel_hlcdc driver, and
>> specifically for the emulated fbdev interface, I received some
>> push-back that my feeble in-driver attempts sho
On 27/06/17 08:39 AM, John Brooks wrote:
> On Mon, Jun 26, 2017 at 03:39:57PM +0200, Christian König wrote:
>> From: Christian König
>>
>> Limit the size of the GART table for the system domain.
>>
>> This saves us a bunch of visible VRAM, but also limitates the maximum BO
>> size we can swap out
From: Dave Airlie
This syncs the amdgpu_drm header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
It brings over the VM and semaphore API changes.
Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit
6d61e70cc
Ignore this, all kinds of patches from wrong tree stuff going on here.
Dave.
On 27 June 2017 at 07:19, Dave Airlie wrote:
> From: Dave Airlie
>
> This adds the corresponding code for libdrm to use the new
> kernel interfaces for semaphores.
>
> This will be used by radv to implement shared sema
On 27/06/17 11:58 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This syncs the amdgpu_drm header with my drm-next branch as of
> 6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
>
> It brings over the VM and semaphore API changes.
>
> Generated using make headers_install.
> Generated from git://peopl
On Mon, Jun 26, 2017 at 06:38:29PM +0900, Michel Dänzer wrote:
> On 24/06/17 02:39 AM, John Brooks wrote:
> > There is no need for page faults to force BOs into visible VRAM if it's
> > full, and the time it takes to do so is great enough to cause noticeable
> > stuttering. Add GTT as a possible pl
74 matches
Mail list logo
