> -Original Message-
> From: Huang Rui [mailto:ray.hu...@amd.com]
> Sent: Friday, May 05, 2017 2:47 PM
> To: Yu, Xiangliang
> Cc: amd-gfx@lists.freedesktop.org; Wang, Daniel(Xiaowei)
>
> Subject: Re: [PATCH 4/6] drm/amdgpu/psp: Do not load asd for SRIOV
>
> On Thu, May 04, 2017 at 02:36
to cover below case:
1. A task gart bind/unbind but not add to adev->gtt_list yet
2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list
Change-Id: Ifb4360e3b68624f2be67fa82100623cf4c451873
Signed-off-by: Roger.He
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu
Reviewed-by: Chunming Zhou
On 2017年05月05日 15:22, Roger.He wrote:
to cover below case:
1. A task gart bind/unbind but not add to adev->gtt_list yet
2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list
Change-Id: Ifb4360e3b68624f2be67fa82100623cf4c451873
Signed-off-by: Roger.H
Looks fine to me, Reviewed-by: Roger.He
BTW, I have noticed SRIOV has more IP resume in first phase, maybe also
needed for bare metal for other ASIC.
Thanks
Roger(Hongbo.He)
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chunming Zhou
Sen
Reviewed-by: Roger.He
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chunming Zhou
Sent: Friday, May 05, 2017 2:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH 2/2] drm/amdgpu: print when gpu reset successed
Am 05.05.2017 um 05:34 schrieb Zhang, Jerry (Junwei):
On 05/04/2017 10:33 PM, Alex Deucher wrote:
rather than defining it locally.
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
drivers/gpu/drm/am
@Pixel, @monk,
found out staging FLR has issue, I'll check it at first.
Let's hold the patch.
Thanks!
Xiangliang Yu
> -Original Message-
> From: Ding, Pixel
> Sent: Thursday, May 04, 2017 4:23 PM
> To: Liu, Monk ; Yu, Xiangliang
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH
Reviewed-by: Christian König
Am 05.05.2017 um 09:33 schrieb zhoucm1:
Reviewed-by: Chunming Zhou
On 2017年05月05日 15:22, Roger.He wrote:
to cover below case:
1. A task gart bind/unbind but not add to adev->gtt_list yet
2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list
Cha
Reviewed-by: Christian König
Am 05.05.2017 um 09:47 schrieb He, Hongbo:
Reviewed-by: Roger.He
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chunming Zhou
Sent: Friday, May 05, 2017 2:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, Davi
We should really improve the order in which blocks are handled.
Having all this special order handling in amdgpu_device.c and for SRIOV
is really not a good idea.
Anyway, patch is Acked-by: Christian König
for now.
Regards,
Christian.
Am 05.05.2017 um 09:46 schrieb He, Hongbo:
Looks fine
Change-Id: Ie5fe90762f75497fab68b913874956bbeab11e72
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index e00ed19..1d9d571 100644
--- a/dr
Change-Id: Ieb05cfa95e4072357e18f631ab71780de0688008
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index a
Signed-off-by: Rex Zhu
Change-Id: I72d61851630e5d4ff5b3236ca33abac6f5b200c6
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 35 --
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 9 +++---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h | 2 +-
drivers/gpu
Change-Id: Ib8681558cabab99da804d1d10987aca63435b1e5
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 43 --
.../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 +
2 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/
Change-Id: Ida8f8168d9600503146b5140ea47c913733888cf
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/include/amd_shared.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 2ccf44e..1d1ac1e 100644
-
Missed these patches the other day. This is some of the recent work
to hook up underlay support.
Shirish S (2):
drm/amd/display: update the YUV plane offsets
drm/amd/display: make dc_commit_surfaces_to_stream() re-entrant
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 85 +-
From: Shirish S
This patch updates the planes default offsets to
the appropriate ones, and aligns the pitch to 64 bits.
BUG=SWDEV-119421
TEST=Boots to UI on jadeite
TEST=
plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500
plane_test --format AR24 --size 500x50 -p --
From: Shirish S
dc_commit_surfaces_to_stream() function currently
is handle's only one plane at a time.
This will not work if multiple planes have to be set to a crtc.
The functionality of dc_commit_surfaces_to_stream() with this patch
is slit into
1. Accumulate and initialise all the surfaces t
On Fri, May 5, 2017 at 2:45 AM, Chunming Zhou wrote:
> the root cause is vram content is lost completely after pci reset.
>
> Change-Id: I012cea984702894410b0f05149fd017bb62b624c
> Signed-off-by: Chunming Zhou
Let's see if it makes sense to change the order globally so we can
avoid things like t
can you check if vega the same
-Original Message-
From: Yu, Xiangliang
Sent: Friday, May 5, 2017 5:18 PM
To: Ding, Pixel ; Liu, Monk ;
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/6] drm/amdgpu: reset GDW, GWS and OA software copy to
update them
@Pixel, @monk,
found out stag
Patch 2 is missing your signed-off-by. With that fixed, the series is:
Reviewed-by: Alex Deucher
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Zhu,
Rex
Sent: Friday, May 05, 2017 8:43 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: Fw: [PATCH 5/5] drm/amd/
Need to use the atomfirmware interface rather than atombios since
soc15 is atomfirmware based.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/am
Update the scratch reg for when the engine is hung.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ato
Add an initial framework for changing the HW priorities of rings. The
framework allows requesting priority changes for the lifetime of an
amdgpu_job. After the job completes the priority will decay to the next
lowest priority for which a request is still valid.
A new ring function set_priority() c
KIQ is now used for baremetal compute initialization. Since it is no
longer compute specific, move the KIQ reg opts to a more general
location.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 55 +++
Hey Everyone,
On one of the previous comments for this series I received feedback that
the register programming should be done through the KIQ. This series has
the relevant changes.
However, register writes that require an srbm_select are not working
correctly. The effect is as if the write never
Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over
other queues on the same pipe. Multiple queues on a pipe are timesliced
so this gives us full precedence over other queues.
Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the
wave as follows:
0x2: CS_
Add WREG32_KIQ_ASYNC() to allow for a caller to perform a register write
without waiting for the result to be commited.
This allows us to queue register writes from a context that cannot
sleep.
It may also be useful for long sequences of register writes performed
through the kiq. Where only the l
Use the [WR]REG32_KIQ() macros when a register operation should go
through the kiq.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 --
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/driver
First step towards enabling kiq register operations from an interrupt
handler
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers
Add a new context creation parameter to express a global context priority.
The priority ranking in descending order is as follows:
* AMDGPU_CTX_PRIORITY_HIGH
* AMDGPU_CTX_PRIORITY_NORMAL
* AMDGPU_CTX_PRIORITY_LOW
The driver will attempt to schedule work to the hardware according to
the priorit
The kiq's srbm window is independent of the MMIO srbm window.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 34 +++---
drivers/gpu/drm/
On Fri, May 5, 2017 at 1:10 PM, Andres Rodriguez wrote:
> Hey Everyone,
>
> On one of the previous comments for this series I received feedback that
> the register programming should be done through the KIQ. This series has
> the relevant changes.
>
> However, register writes that require an srbm_
We ran into a similar problem when we played with priorities on KFD
queues. You can't change an MQD of a currently mapped queue. To change a
queue priority we need to unmap it, update the MQD, and then map it again.
I wonder if a queue can change its own priority by using register write
commands i
This works perfectly fine if I use MMIO writes. But KIQ breaks when done
over KIQ, which is why I find it weird.
Regards,
Andres
On 2017-05-05 06:57 PM, Felix Kuehling wrote:
We ran into a similar problem when we played with priorities on KFD
queues. You can't change an MQD of a currently mapp
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