, 2021 11:48 PM
To: Zhou, Peng Ju ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/8] drm/amdgpu: change MMHUB register access from MMIO to
RLCG
Am 2021-04-15 um 3:25 a.m. schrieb Zhou, Peng Ju:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Felix
> Thanks for your pr
keep our original workaround.
>
> Do you agree?
>
>
> --
> BW
> Pengju Zhou
>
>
>
> -Original Message-
> From: Zhou, Peng Ju
> Sent: Friday, April 9, 2021 11:36 AM
> To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 1
; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 1/8] drm/amdgpu: change MMHUB register access from MMIO to
RLCG
[AMD Official Use Only - Internal Distribution Only]
Hi Felix
That is a great idea, I will try it.
--
BW
Pengju Zhou
---
Ju ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/8] drm/amdgpu: change MMHUB register access from MMIO to
RLCG
Given the number of call-sites being modified in this patch series, would it be
easier (and more maintainable) to change the behaviour or the regular register
macros and add
Given the number of call-sites being modified in this patch series,
would it be easier (and more maintainable) to change the behaviour or
the regular register macros and add NO_RLC versions for the exceptions,
similar to NO_KIQ?
Regards,
Felix
Am 2021-04-08 um 6:21 a.m. schrieb Peng Ju Zhou:
>
