Re: [PATCH 4/4] drm/amdgpu: Implement OS triggered MCBP(v4)

2022-09-19 Thread Luben Tuikov
Inline: On 2022-09-15 04:16, jiadong@amd.com wrote: > From: "Jiadong.Zhu" > > Trigger Mid-Command Buffer Preemption according to the priority of the > software > rings and the hw fence signalling condition. > > The muxer saves the locations of the indirect buffer frames from the software >

[PATCH 4/4] drm/amdgpu: Implement OS triggered MCBP(v4)

2022-09-15 Thread jiadong.zhu
From: "Jiadong.Zhu" Trigger Mid-Command Buffer Preemption according to the priority of the software rings and the hw fence signalling condition. The muxer saves the locations of the indirect buffer frames from the software ring together with the fence sequence number in its fifo queue, and pops