Re: [PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-20 Thread shaoyunl
I see.  So this change Reviewed-by: shaoyun liu On 2020-01-20 1:40 p.m., Felix Kuehling wrote: On 2020-01-20 1:28 p.m., shaoyunl wrote: On 2020-01-20 12:58 p.m., Felix Kuehling wrote: On 2020-01-20 12:47 p.m., shaoyunl wrote: comments in line . On 2020-01-17 8:37 p.m., Felix Kuehling wro

Re: [PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-20 Thread Felix Kuehling
On 2020-01-20 1:28 p.m., shaoyunl wrote: On 2020-01-20 12:58 p.m., Felix Kuehling wrote: On 2020-01-20 12:47 p.m., shaoyunl wrote: comments in line . On 2020-01-17 8:37 p.m., Felix Kuehling wrote: Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same T

Re: [PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-20 Thread shaoyunl
On 2020-01-20 12:58 p.m., Felix Kuehling wrote: On 2020-01-20 12:47 p.m., shaoyunl wrote: comments in line . On 2020-01-17 8:37 p.m., Felix Kuehling wrote: Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries

Re: [PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-20 Thread Felix Kuehling
On 2020-01-20 12:47 p.m., shaoyunl wrote: comments in line . On 2020-01-17 8:37 p.m., Felix Kuehling wrote: Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the he

Re: [PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-20 Thread shaoyunl
comments in line . On 2020-01-17 8:37 p.m., Felix Kuehling wrote: Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix

RE: [PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-20 Thread Zeng, Oak
3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix this

[PATCH 3/3] drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

2020-01-17 Thread Felix Kuehling
Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix this race condition, perform another TLB flush after the heavy-weigh