Re: [PATCH 1/5] drm/amd: Introduce additional IPS debug flags

On 2024-08-19 10:41, Harry Wentland wrote: On 2024-08-16 18:57, sunpeng...@amd.com wrote: From: Leo Li [Why] Idle power states (IPS) describe levels of power-gating within DCN. DM and DC is responsible for ensuring that we are out of IPS before any DCN programming happens. Any DCN progra

Re: [PATCH 1/5] drm/amd: Introduce additional IPS debug flags

On 2024-08-16 18:57, sunpeng...@amd.com wrote: > From: Leo Li > > [Why] > > Idle power states (IPS) describe levels of power-gating within DCN. DM > and DC is responsible for ensuring that we are out of IPS before any DCN > programming happens. Any DCN programming while we're in IPS leads to

[PATCH 1/5] drm/amd: Introduce additional IPS debug flags

From: Leo Li [Why] Idle power states (IPS) describe levels of power-gating within DCN. DM and DC is responsible for ensuring that we are out of IPS before any DCN programming happens. Any DCN programming while we're in IPS leads to undefined behavior (mostly hangs). Because IPS intersects with