Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

al Message- From: Christian König Sent: Monday, June 24, 2024 7:58 PM To: Jian, Jane ; Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush Am 24.06.24 um 11:13 sc

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush Am 24.06.24 um 11:13 schrieb Jane Jian: > [WHY] > sriov has the higher bit violation when flushing tlb > >

Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

Am 24.06.24 um 11:13 schrieb Jane Jian: [WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd [TODO] later will add the norma

Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

ions. Regards, Christian. Thanks, Jane -Original Message- From: Christian König Sent: Monday, June 24, 2024 5:35 PM To: Jian, Jane ; Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

. Thanks, Jane -Original Message- From: Christian König Sent: Monday, June 24, 2024 5:35 PM To: Jian, Jane ; Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

Am 24.06.24 um 11:13 schrieb Jane Jian: [WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd [TODO] later will add the norma

[PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd [TODO] later will add the normalization in sriovw/rreg after fixing bugs

Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

On 6/21/2024 1:45 PM, Jane Jian wrote: > [WHY] > sriov has the higher bit violation when flushing tlb > > [HOW] > normalize the registers to keep lower 16-bit(dword aligned) to aviod higher > bit violation > RLCG will mask xcd out and always assume it's accessing its own xcd > > [TODO] > late

[PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd [TODO] later will add the normalization in sriovw/rreg after fixing bugs

[PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd [TODO] later will add the normalization in sriovw/rreg after fixing bugs

[PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd [TODO] later will add the normalization in sriovw/rreg after fixing bugs

Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov

On 6/17/2024 3:41 PM, Jane Jian wrote: > [WHY] > sriov has the higher bit violation when flushing tlb > > [HOW] > normalize the registers to keep lower 16-bit(dword aligned) to aviod higher > bit violation > RLCG will mask xcd out and always assume it's accessing its own xcd > > also fix the

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov

, Qing (Mark) Subject: RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov [AMD Official Use Only - AMD Internal Distribution Only] Ping on this... Thanks, Jane -Original Message- From: Jane Jian Sent: Monday, June 17, 2024 6:11 PM To: Lazar, Lijo ; Chang

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov

: normalize registers as local xcc to read/write under sriov [WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd also fix the

[PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov

[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd also fix the typo in sriov_w/rreg: for KIQ case, use xcc with xcc_id to r

[PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov

[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd also fix the typo in sriov_w/rreg: for KIQ case, use xcc with xcc_id to r