Re: [PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

2021-05-13 Thread Christian König
Am 12.05.21 um 20:40 schrieb philip yang: On 2021-05-12 11:54 a.m., Felix Kuehling wrote: Am 2021-05-12 um 8:38 a.m. schrieb Christian König: Am 12.05.21 um 14:34 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 a

Re: [PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

2021-05-12 Thread Felix Kuehling
Am 2021-05-12 um 2:40 p.m. schrieb philip yang: > > > On 2021-05-12 11:54 a.m., Felix Kuehling wrote: >> Am 2021-05-12 um 8:38 a.m. schrieb Christian König: >>> Am 12.05.21 um 14:34 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously

Re: [PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

2021-05-12 Thread philip yang
On 2021-05-12 11:54 a.m., Felix Kuehling wrote: Am 2021-05-12 um 8:38 a.m. schrieb Christian König: Am 12.05.21 um 14:34 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If prev

Re: [PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

2021-05-12 Thread Felix Kuehling
Am 2021-05-12 um 8:38 a.m. schrieb Christian König: > > > Am 12.05.21 um 14:34 schrieb Philip Yang: >> Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. >> If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this >> requires TLB flush, otherwise page table walker w

Re: [PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

2021-05-12 Thread Christian König
Am 12.05.21 um 14:34 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping t

[PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

2021-05-12 Thread Philip Yang
Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return free_table flag to indicate the previo