[AMD Official Use Only - AMD Internal Distribution Only]
>-Original Message-
>From: Christian König
>Sent: Monday, June 24, 2024 11:31 AM
>To: Slivka, Danijel ; amd-gfx@lists.freedesktop.org;
>Prica, Nikola
>Subject: Re: [PATCH] drm/amdgpu: clear RB_OVERFLOW bi
Am 24.06.24 um 08:58 schrieb Danijel Slivka:
Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so th
Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear
