On Tue, Jun 25, 2024 at 2:32 PM Aurabindo Pillai
wrote:
>
> Add some register offsets that are required for Display DCC on DCN401
>
> Fixes: 000342e3a22 ("drm/amd: Add reg definitions for DCN401 DCC")
> Reported-by: Tom St Denis
> Signed-off-by: Aurabindo Pillai
Acked-by: Alex Deucher
> ---
>
Add some register offsets that are required for Display DCC on DCN401
Fixes: 000342e3a22 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis
Signed-off-by: Aurabindo Pillai
---
.../include/asic_reg/dcn/dcn_4_1_0_offset.h| 18 ++
1 file changed, 18 inser