This reverts commit
2a69ae1e1354 ("drm/amd/display: Use HW lock mgr for PSR1")
Because it may cause system hang while connect with two edp panel.
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletion
function before DCN32.
We remov eDP power down in dcn32_disable_link_output().
Reviewed-by: Charlene Liu
Signed-off-by: Yiling Chen
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a
d one first.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3720
Fixes: fa57924c76d9 ("drm/amd/display: Refactor function
dm_dp_mst_is_port_support_mode()")
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Jerry Zuo
Signed-off-by: Wayne Lin
Sig
[Why]
Without the dmub hw lock, it may cause the lock timeout issue
while do modeset on PSR1 eDP panel.
[How]
Allow dmub hw lock for PSR1.
Reviewed-by: Sun peng Li
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Gabe Teeger
[why]
Underflow and flickering was occuring due to high scaling ratios
when resizing videos.
[how]
Limit the scaling ratios by increasing the max scaling factor
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Gabe Teeger
Signed-off-by: Tom Chung
---
.../drm/amd/display/dc
Signed-off-by: Tom Chung
---
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
inde
eferences in DML2.1 wrapper.
Reviewed-by: Austin Zheng
Reviewed-by: Dillon Varone
Signed-off-by: Rafal Ostrowski
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 16 +-
.../dc/dml2/dml21/dml21_translation_helper.c | 77 --
.../dc/dml2/dml21/dml21_translation_helper
ps between them.
Fixes: a7c0cad0dc06 ("drm/amd/display: ensure async flips are only accepted for
fast updates")
Reviewed-by: Tom Chung
Signed-off-by: Leo Li
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++
1 file changed, 23 insertions
From: Charlene Liu
[why & how]
this is to init to HW real DTBCLK.
and use real HW DTBCLK status to update internal logic state
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Martin Leung
Signed-off-by: Charlene Liu
Signed-off-by: Ausef Yousof
Signed-off-by: Tom Chung
---
.../displa
refactoring DML2.1
Acked-by: Wayne Lin
Reviewed-by: Martin Leung
Signed-off-by: Ryan Seto
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
hpd_pending is true.
3. check if 2 lane supported when it is alt mode
Reviewed-by: Wenjing Liu
Reviewed-by: Meenakshikumar Somasundaram
Signed-off-by: Peichen Huang
Signed-off-by: Tom Chung
---
.../amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c| 5 +++--
drivers/gpu/drm/amd/display/dc/link
From: Dennis Chan
[why & how]
Revised Replay Full screen video Pseudo vblank control.
Reviewed-by: Allen Li
Signed-off-by: Dennis Chan
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 4 ++--
drivers/gpu/drm/amd/display/modules/power/power_helpe
that no
functionality is affected, and the code is simplified.
Reviewed-by: Martin Leung
Signed-off-by: Karthi Kandasamy
Signed-off-by: Tom Chung
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 85 ---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 -
2 files changed, 87
From: Austin Zheng
[Why & How]
Add several DML21 fixes
Reviewed-by: Wenjing Liu
Signed-off-by: Austin Zheng
Signed-off-by: Tom Chung
---
.../src/dml2_core/dml2_core_dcn4_calcs.c | 107 --
.../src/dml2_core/dml2_core_shared_types.h| 6 +-
.../dml21/src/dml2_
From: Robin Chen
[Why & How]
Add a new flag in replay_config to indicate the replay
low hz status.
Reviewed-by: Allen Li
Signed-off-by: Robin Chen
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
iting for panel to
exit PSR1, before programming hw for CRC generation.
Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for
older ASICs")
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3743
Reviewed-by: Tom Chung
Signed-off-by: Leo Li
Signed-of
rruption issue
which it fixed.
Reviewed-by: Charlene Liu
Signed-off-by: Nicholas Susanto
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
From: Dillon Varone
[WHY&HOW]
BIOS table will not always contain accurate UMC channel info when
harvesting is enabled, so get the correct info from SMU.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h
From: Alex Hung
[WHAT & HOW]
Variables, used as denominators and maybe not assigned to other values,
should be initialized to non-zero to avoid DIVIDE_BY_ZERO, as reported
by Coverity.
Reviewed-by: Austin Zheng
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Tom C
. Additionally, add another parameter to specify whether to skip the
default reset of crc engine.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Tom Chung
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +-
drivers/gpu/drm
handled by the driver only
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Tom Chung
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 56 +--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 9 +++
2 files changed, 49 insertions(+), 16 deletions(-)
diff --git a/
From: Jack Chang
[Why & How]
Build-up get/reset desync error count interface and implement the functions.
Reviewed-by: ChunTao Tso
Reviewed-by: Robin Chen
Signed-off-by: Jack Chang
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc_types.h| 2 ++
.../drm
.
Reviewed-by: Wenjing Liu
Signed-off-by: Michael Strauss
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 9 +
.../amd/display/dc/link/accessories/link_dp_cts.c | 4 ++--
.../link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 2 +-
drivers/gpu/drm/amd
From: Taimur Hassan
Refactoring some flags for replay
Acked-by: Wayne Lin
Signed-off-by: Taimur Hassan
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
Signed-off-by: Tom Chung
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 16 ++
drivers/gpu/drm/amd/display/dc/core/dc.c | 22 +++
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 +++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc
w hz
Ryan Seto (1):
drm/amd/display: 3.2.316
Sung Lee (1):
drm/amd/display: Log Hard Min Clocks and Phantom Pipe Status
Taimur Hassan (1):
drm/amd/display: [FW Promotion] Release 0.0.248.0
Tom Chung (1):
drm/amd/display: Use HW lock mgr for PSR1
Wayne Lin (4):
drm/amd/display: Val
Reviewed-by: Tom Chung
On 11/5/2024 10:01 PM, Zicheng Qu wrote:
This commit addresses a null pointer dereference issue in
dcn20_program_pipe(). Previously, commit 8e4ed3cf1642 ("drm/amd/display:
Add null check for pipe_ctx->plane_state in dcn20_program_pipe")
partially fixed the
Reviewed-by: Tom Chung
On 11/5/2024 10:01 PM, Zicheng Qu wrote:
This commit addresses a null pointer dereference issue in
hwss_setup_dpp(). The issue could occur when pipe_ctx->plane_state is
null. The fix adds a check to ensure `pipe_ctx->plane_state` is not null
before accessing
From: Lohita Mudimela
[Why]
For Header related changes for core
[How]
Refactoring if and endif statements to enable DC_LOGGER
Reviewed-by: Mounika Adhuri
Reviewed-by: Alvin Lee
Signed-off-by: Lohita Mudimela
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn31
From: Taimur Hassan
Add some scruct for secure display.
Acked-by: Wayne Lin
Signed-off-by: Taimur Hassan
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 +++
1 file changed, 44 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd
eira
Signed-off-by: Alex Hung
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c| 1 -
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 2 --
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 --
drivers/gpu/drm/amd/displa
Lin
Signed-off-by: Aric Cyr
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 412cdb01a61a..72adbab589f5 100644
--- a/drivers/gpu
dscl_prog_data. This ensures
that each display can have its own sharpness setting.
Reviewed-by: Ilya Bakoulin
Signed-off-by: Samson Tam
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 3 ++-
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 3
From: Ovidiu Bunea
[why & how]
DSC may be power gated when coming out of S0i3, so avoid polling
DSC registers since it will fail anyways. Only read if it is known
that DSC is in use.
Reviewed-by: Charlene Liu
Signed-off-by: Ovidiu Bunea
Signed-off-by: Tom Chung
---
.../drm/amd/displa
and add them in DC
Reviewed-by: Alvin Lee
Signed-off-by: Aurabindo Pillai
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 8 ++--
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
to populate dscl_prog_data
Populate taps in spl_get_optimal_number_of_taps
Reviewed-by: Alvin Lee
Signed-off-by: Samson Tam
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
]
Use colours that only have 0 or MAX values in each component
Reviewed-by: Alvin Lee
Signed-off-by: Joshua Aberback
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Alex Hung
[WHAT & HOW]
The variable "ips_supported" is redundant and we can return from
dcn35_smu_get_ips_supported directly.
This fixes 1 UNUSED_VALUE issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Tom Chung
---
drive
ed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
.../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/d
g, so there
is another issue generic to that sequence that needs to be
investigated.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Ovidiu Bunea
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c | 1 +
m/amd/display: Add periodic detection for IPS")
Reviewed-by: Roman Li
Signed-off-by: Fangzhi Zuo
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu
From: Dillon Varone
[WHY&HOW]
Adds support for P-State stall timeout detection in DCHUBBUB.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
.../dc/dml2/dml21/inc/dml_top_dchub_registers.h | 1 +
.../dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
From: Hansen Dsouza
[Why]
Spread on DPREFCLK by 0.3 percent can have a negative effect on sink
when PHY SSC is also spread by 0.3 percent
[How]
Add boot option for DMU to lower PHY SSC
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Hansen Dsouza
Signed-off-by: Tom Chung
---
drivers/gpu/drm
gned-off-by: Ovidiu Bunea
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
.../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 3 ++-
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fix polling DSC registers during S0i3
- Fix idle optimizations entry log
- Change MPC Tree visual confirm colours
- Fix underflow when playing 8K video in full screen mode
- Optimize power up sequence for specific
Reviewed-by: Tom Chung
On 9/17/2024 9:13 PM, Srinivasan Shanmugam wrote:
Correct the parameter descriptor for the function
`dc_process_dmub_dpia_set_tps_notification` to match the actual
parameters used.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5768
Reviewed-by: Tom Chung
On 9/4/2024 3:43 PM, Srinivasan Shanmugam wrote:
Added a descriptor for the 'program_isharp_1dlut' parameter, which is a
flag used to determine whether to program the isharp 1D LUT.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/
Reviewed-by: Tom Chung
On 8/29/2024 9:17 PM, Srinivasan Shanmugam wrote:
This commit addresses a missing kdoc for the 'bs_coeffs_updated'
parameter in the 'dpp401_dscl_program_isharp' function. The
'bs_coeffs_updated' is a flag indicating whether the Blur an
On 8/28/2024 7:25 PM, Srinivasan Shanmugam wrote:
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:961:
warning: Function parameter or struct member 'bs_coeffs_updated' not described
in 'dpp401_dscl_program_isharp'
Cc: To
Reviewed-by: Tom Chung
On 8/12/2024 6:40 PM, Srinivasan Shanmugam wrote:
The descriptor for `hwss_wait_for_all_blank_complete` was previously
misaligned with the actual implementation. This commit refines the
descriptor to reflect the implementation of
`hwss_wait_for_all_blank_complete`
Fixes
Reviewed-by: Tom Chung
On 8/7/2024 9:20 AM, Srinivasan Shanmugam wrote:
This commit adds a null check for the 'afb' variable in the
amdgpu_dm_update_cursor function. Previously, 'afb' was assumed to be
null at line 8388, but was used later in the code without a nu
Reviewed-by: Tom Chung
On 8/7/2024 9:20 AM, Srinivasan Shanmugam wrote:
This commit adds a null check for the 'afb' variable in the
amdgpu_dm_plane_handle_cursor_update function. Previously, 'afb' was
assumed to be null, but was used later in the code without a nu
position for AS-SDP
- Update to using new dccg callbacks
- Enable otg synchronization logic for DCN321
- Disable DCN401 UCLK P-State support on full updates
Acked-by: Wayne Lin
Signed-off-by: Martin Leung
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1
From: Rodrigo Siqueira
[why & how]
Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, since
those macros are not necessary anymore at the dpp1 set degamma. Those
are part of an old implementation.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom C
nk: https://gitlab.freedesktop.org/drm/amd/-/issues/2247
Reviewed-by: Harry Wentland
Fixes: 9d84c7ef8a87 ("drm/amd/display: Correct cursor position on horizontal
mirror")
Signed-off-by: Melissa Wen
Signed-off-by: Hamza Mahfooz
Signed-off-by: Alex Deucher
Signed-off-by: Tom Chung
Cc: sta...@vger.kernel.o
patch.
Fixes: 9d84c7ef8a87 ("drm/amd/display: Correct cursor position on horizontal
mirror")
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn1
rm/amd/display: Add driver support for future FAMS
versions")
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Rodrigo Siqueira
[why & how]
Remove force_backlight_start_level since it is never used.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/dis
From: Charlene Liu
[why & how]
this is to remove redundant msg to pmfw at boot/resume
since bios already power up dcn.
Reviewed-by: Chris Park
Signed-off-by: Charlene Liu
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 7 +--
1 file change
in dcn321.
Fixes: 5f0c74915815 ("drm/amd/display: Fix for otg synchronization logic")
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Signed-off-by: Loan Chen
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource
From: Dillon Varone
[WHY&HOW]
Set max VTotal cap for dcn401 because VTotal
register is only 16 bits wide on dcn401.
Reviewed-by: Chris Park
Signed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file change
perform any strictly required outstanding programming.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 121 +
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 123 ++
.../amd/display/dc
f-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index b604c8886ef4..ac0a21ac
k the transition as seamless.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq
Signed-off-by: Robin Chen
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index
From: Roman Li
[Why]
%d specifier is used for printing unsigned values.
It can result in negative values in logs for unsigned variables.
[How]
Replace %d with %u for unsigned.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Roman Li
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display
From: Wayne Lin
[why & how]
Make sure plane_state is not null before calling a function
that dereferences it. Besides, remove redundant codes.
Reviewed-by: Alex Hung
Signed-off-by: Wayne Lin
Signed-off-by: Tom Chung
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c
From: Rodrigo Siqueira
[why & how]
Change the order of the pipe_ctx->plane_state check to ensure that
plane_state is not null before accessing it.
Reviewed-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
From: Muhammad Ahmed
[why & how]
HW removed this w/a, but we will still keep it to avoid regression.
but return in test mode.
Reviewed-by: Charlene Liu
Signed-off-by: Muhammad Ahmed
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 3 +++
1
From: Aurabindo Pillai
[why & how]
print additional info for MALL related calculations and DMCUB messaging
to aid debugging.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
pipes.
Reviewed-by: Alvin Lee
Signed-off-by: Austin Zheng
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 28 ++
.../display/dc/hubbub/dcn401/dcn401_hubbub.c | 23 +
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 91 +++
.../amd/display/dc
es to
"dcn35_apply_idle_power_optimizations".)
This fixes 1 FORWARD_NULL issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
dif
From: Hansen Dsouza
[Why and how]
Update to using new dccg callbacks
Reviewed-by: Chris Park
Signed-off-by: Hansen Dsouza
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
d-off-by: Tom Chung
---
.../amd/display/dc/hwss/dcn32/dcn32_init.c| 1 -
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 46 ---
.../amd/display/dc/hwss/dcn401/dcn401_init.c | 2 +-
3 files changed, 21 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/displ
even if dispclk can't reach Vmin.
Reviewed-by: Austin Zheng
Signed-off-by: Wenjing Liu
Signed-off-by: Tom Chung
---
.../dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 14 +-
.../display/dc/dml2/dml21/src/dml2_top/dml_top.c | 13 +++--
2 files changed, 20 insert
From: Wenjing Liu
[why & how]
There is a coding error which causes incorrect variables to be assigned
in DML21 phase 5.
Reviewed-by: Austin Zheng
Signed-off-by: Wenjing Liu
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c | 4 ++--
1 file change
- Fix some cursor issue
- Fix print format specifiers in DC_LOG_IPS
- Fix minor coding errors in dml21 phase 5
- Improve FAM control for DCN401
- Add null pointer checks for some code
- Refactor 3DLUT for non-DMA
- Optimize vstartup position for AS-SDP
- Update to using new dccg callbacks
- Enable
Reviewed-by: Tom Chung
On 7/31/2024 3:57 PM, Srinivasan Shanmugam wrote:
This commit adds a null check for the set_output_gamma function pointer
in the dcn401_set_output_transfer_func function. Previously,
set_output_gamma was being checked for null, but then it was being
dereferenced without
Reviewed-by: Tom Chung
On 7/31/2024 3:57 PM, Srinivasan Shanmugam wrote:
This commit adds a null check for the set_output_gamma function pointer
in the dcn32_set_output_transfer_func function. Previously,
set_output_gamma was being checked for null, but then it was being
dereferenced without
Reviewed-by: Tom Chung
On 7/31/2024 3:57 PM, Srinivasan Shanmugam wrote:
This commit adds a null check for the set_output_gamma function pointer
in the dcn20_set_output_transfer_func function. Previously,
set_output_gamma was being checked for null at line 1030, but then it
was being
Reviewed-by: Tom Chung
On 7/30/2024 12:11 PM, Srinivasan Shanmugam wrote:
This commit corrects the function comment for
'dpp401_dscl_program_isharp' in 'dcn401_dpp_dscl.c'. The comment
previously included a description for a non-existent parameter
'bs_coeffs
Reviewed-by: Tom Chung
On 7/26/2024 10:03 PM, Srinivasan Shanmugam wrote:
This commit adds a null check for 'stream_status' in the function
'planes_changed_for_existing_stream'. Previously, the code assumed
'stream_status' could be null, but did not handle the c
Reviewed-by: Tom Chung
On 7/25/2024 10:54 AM, Srinivasan Shanmugam wrote:
This commit addresses a null pointer dereference issue in the
`dcn20_program_pipe` function. The issue could occur when
`pipe_ctx->plane_state` is null.
The fix adds a check to ensure `pipe_ctx->plane_state` is no
Reviewed-by: Tom Chung
On 7/25/2024 10:54 AM, Srinivasan Shanmugam wrote:
This commit addresses a null pointer dereference issue in the
`commit_planes_for_stream` function at line 4140. The issue could occur
when `top_pipe_to_program` is null.
The fix adds a check to ensure
Reviewed-by: Tom Chung
On 7/22/2024 7:48 PM, Srinivasan Shanmugam wrote:
This commit adds a null check for the set_output_gamma function pointer
in the dcn30_set_output_transfer_func function. Previously,
set_output_gamma was being checked for nullity at line 386, but then it
was being
_output_gamma(mpc, mpcc_id, params);
Then it will crash
402 return ret;
403 }
Fixes: d99f13878d6f ("drm/amd/display: Add DCN3 HWSEQ")
Reported-by: Dan Carpenter
Cc: Tom Chung
Cc: Rodrigo Siqueira
Cc: Roman Li
Cc: H
Reviewed-by: Tom Chung
On 7/22/2024 9:46 AM, Srinivasan Shanmugam wrote:
This commit addresses a potential null pointer dereference issue in the
`dcn32_acquire_idle_pipe_for_head_pipe_in_layer` function. The issue
could occur when `head_pipe` is null.
The fix adds a check to ensure `head_pipe
Reviewed-by: Tom Chung
On 7/22/2024 9:46 AM, Srinivasan Shanmugam wrote:
This commit addresses a potential null pointer dereference issue in the
`dcn201_acquire_free_pipe_for_layer` function. The issue could occur
when `head_pipe` is null.
The fix adds a check to ensure `head_pipe` is not
Reviewed-by: Tom Chung
On 7/21/2024 2:22 PM, Srinivasan Shanmugam wrote:
This commit addresses a potential index out of bounds issue in the
`cm3_helper_translate_curve_to_hw_format` function in the DCN30 color
management module. The issue could occur when the index 'i' exceeds the
Reviewed-by: Tom Chung
On 7/21/2024 2:22 PM, Srinivasan Shanmugam wrote:
This commit addresses a potential index out of bounds issue in the
`cm3_helper_translate_curve_to_degamma_hw_format` function in the DCN30
color management module. The issue could occur when the index 'i'
e
Reviewed-by: Tom Chung
On 7/21/2024 2:22 PM, Srinivasan Shanmugam wrote:
Fixes index out of bounds issue in
`cm_helper_translate_curve_to_degamma_hw_format` function. The issue
could occur when the index 'i' exceeds the number of transfer function
points (TRANSFER_FUNC_POINTS).
The
Reviewed-by: Tom Chung
On 7/20/2024 12:12 AM, Srinivasan Shanmugam wrote:
'stream_enc_regs' array is an array of dcn10_stream_enc_registers
structures. The array is initialized with four elements, corresponding
to the four calls to stream_enc_regs() in the array initializer. This
Reviewed-by: Tom Chung
On 7/18/2024 12:03 PM, Srinivasan Shanmugam wrote:
Fixes the below with gcc W=1:
Function parameter or struct member 'pstate_keepout' not described in
'optc1_program_timing'
Cc: Tom Chung
Cc: Rodrigo Siqueira
Cc: Roman Li
Cc: Alex Hung
Cc:
Reviewed-by: Tom Chung
On 5/15/2024 11:23 PM, Srinivasan Shanmugam wrote:
The parameters segment_width and last_segment_width are used to control
the configuration of the Output Plane Processor (OPP), specifically the
width of each segment that the display is divided into and the width of
the
This patch looks good to me.
Reviewed-by: Tom Chung
On 5/9/2024 9:55 AM, Mario Limonciello wrote:
The pixel_clock_mhz property is populated in amdgpu_dm when Freesync is setup,
but it is not used anywhere in amdgpu_dm. Remove the dead code.
Cc:chiahsuan.ch...@amd.com
Signed-off-by: Mario
component folder
- Refactor input mode programming for DIG FIFO
- Reset DSC clock in post unlock update
- Clean-up recout calculation for visual confirm
- Enable urgent latency adjustments for DCN35
Acked-by: Tom Chung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file
From: Alex Hung
[Why & How]
dml_stream_idx will be -1 when it is not found. Check and skip in such a
case as -1 is not a valid array index.
This fixes a NEGATIVE_RETURNS issue reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Tom Chung
Signed-off-by: Alex Hung
---
drivers/gpu
ABM HW caps
since not all ASICs have the same number of cure segments and
bins
Acked-by: Tom Chung
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 139 ++
1 file changed, 139 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc
cess
array, Coverity suspects index invalid.
[How]
Change varaible type to uint32_t.
Reviewed-by: Alex Hung
Reviewed-by: Harry Wentland
Acked-by: Tom Chung
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
-by: Harry Wentland
Acked-by: Tom Chung
Signed-off-by: Alex Hung
---
.../dc/dml2/dml21/dml21_translation_helper.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
b/drivers/gpu/drm/
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