From: Jiadong Zhu
Implement sdma queue reset callback via SMU interface.
v2: Leverage inst_stop/start functions in reset sequence.
Use GET_INST for physical SDMA instance.
Disable apu for sdma reset.
v3: Rephrase error prints.
v4: Remove redundant prints. Remove setting PREEMPT registers
From: Jiadong Zhu
Implement sdma soft reset by sending MSG_ResetSDMA on smu 13.0.6.
v2: Add firmware version for the reset message.
v3: Add ip version check. Print inst_mask on failure.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15
drivers/gpu
From: Jiadong Zhu
update smu header for sdma soft reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu
From: Jiadong Zhu
Implement sdma queue reset callback via SMU interface.
v2: Leverage inst_stop/start functions in reset sequence.
Use GET_INST for physical SDMA instance.
Disable apu for sdma reset.
v3: Rephrase error prints.
v4: Remove redundant prints.
Signed-off-by: Jiadong Zhu
---
From: Jiadong Zhu
Implement sdma soft reset by sending MSG_ResetSDMA on smu 13.0.6.
v2: Add firmware version for the reset message.
v3: Add ip version check. Print inst_mask on failure.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15
drivers/gpu
From: Jiadong Zhu
Implement sdma queue reset callback via SMU interface.
v2: Leverage inst_stop/start functions in reset sequence.
Use GET_INST for physical SDMA instance.
Disable apu for sdma reset.
v3: Rephrase error prints.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/
From: Jiadong Zhu
update smu header for sdma soft reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu
From: Jiadong Zhu
Implement sdma queue reset callback via SMU interface.
v2: Leverage inst_stop/start functions in reset sequence.
Use GET_INST for physical SDMA instance.
Disable apu for sdma reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 97
From: Jiadong Zhu
Implement sdma soft reset by sending MSG_ResetSDMA on smu 13.0.6.
v2: add firmware version for the reset message.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15 +
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
drivers/gp
From: Jiadong Zhu
update smu header for sdma soft reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu
From: Jiadong Zhu
update smu header for sdma soft reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu
From: Jiadong Zhu
Implement sdma queue reset callback via SMU interface.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 137 ---
1 file changed, 123 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/g
From: Jiadong Zhu
Implement sdma soft reset by sending MSG_ResetSDMA on smu 13.0.6.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15 +++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c|
From: Jiadong Zhu
Implement sdma queue reset callback via MMIO.
v2: enter/exit safemode for mmio queue reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 91 ++
1 file changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v
From: Jiadong Zhu
Extract the resume sequence from sdma_v5_2_gfx_resume for
starting/restarting an individual instance.
Signed-off-by: Jiadong Zhu
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 247 ++---
1 file changed, 136 insertions(+), 111 deletion
From: Jiadong Zhu
Implement sdma queue reset callback via MMIO.
v2: enter/exit safemode when sdma queue reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_
From: Jiadong Zhu
Extract the resume sequence from sdma_v5_0_gfx_resume for
starting/restarting an individual instance.
Signed-off-by: Jiadong Zhu
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 253 ++---
1 file changed, 138 insertions(+), 115 deletion
From: Jiadong Zhu
Implement sdma queue reset callback via MMIO.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
From: Jiadong Zhu
Implement sdma queue reset callback via MMIO.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 86 +-
1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amd
From: Jiadong Zhu
Extract the resume sequence from sdma_v5_0_gfx_resume for
starting/restarting an individual instance.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 253 ++---
1 file changed, 138 insertions(+), 115 deletions(-)
diff --git a/drive
From: Jiadong Zhu
Extract the resume sequence from sdma_v5_2_gfx_resume for
starting/restarting an individual instance.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 247 ++---
1 file changed, 136 insertions(+), 111 deletions(-)
diff --git a/drive
From: Jiadong Zhu
Implement sdma queue reset callback using mes_reset_queue_mmio.
v2: check instance id before reset queue.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd
From: Jiadong Zhu
Reset sdma queue through mmio based on me_id and queue_id.
v2: simplify callflows and register calculation.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 27 -
2 files changed
From: Jiadong Zhu
Extract the resume sequence for individual sdma instance from
sdma_v6_0_gfx_resume.
The function could be used for start/restart scenario on a certain instance.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 240 ++---
1 file chan
From: Jiadong Zhu
Implement sdma queue reset callback using mes_reset_queue_mmio.
Extract sdma resume sequence from sdma_v6_0_gfx_resume for queue restarting.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 266 +++--
1 file changed, 157 insertions(+
From: Jiadong Zhu
Reset sdma queue through mmio based on me_id and queue_id.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 53 -
2 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/d
From: Jiadong Zhu
The function amdgpu_ring_mux_start_ib shall not be called on
high priority rings even if mcbp is disabled. Otherwise there
maybe leak from the chunks of the ring mux.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 4 ++--
1 file changed, 2 inser
From: Jiadong Zhu
The job's embedded fence is dma_fence which shall not be conversed
to amdgpu_fence. The start timestamp shall be saved on job for
hw_fence.
v2: optimize get_fence_start_time.
v3: set start time only when mcbp enabled.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu
From: Jiadong Zhu
The job's embedded fence is dma_fence which shall not be conversed
to amdgpu_fence. The start timestamp shall be saved on job for
hw_fence.
v2: optimize get_fence_start_time.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 31 --
From: Jiadong Zhu
The job's embedded fence is dma_fence which shall not be conversed
to amdgpu_fence. The start timestamp shall be saved on job for
hw_fence.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 33 ---
drivers/gpu/drm/amd/amdgpu/amdgpu
From: Jiadong Zhu
Disable MCBP(mid command buffer preemption) by default as old Mesa
hangs with it. We shall not enable the feature that breaks old usermode
driver.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4
1 file changed, 4 deletions(-)
diff --git a/
From: Jiadong Zhu
Set the default reset method to mode2 for SMU IP v14.0.0
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 8c6cab641a1c..ebf99406
From: Jiadong Zhu
Add tmz support for GC 11.5.0.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index a02992bff6af..2dce338b0f1e 100644
From: Jiadong Zhu
PMFW will handle the features disablement properly for gpu reset case,
driver involvement may cause some unexpected issues.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/g
From: Jiadong Zhu
The parameter amdgpu_mcbp shall have priority against the default value
calculated from the chip version.
User could disable mcbp by setting the parameter mcbp as zero.
v2: do not trigger preemption in sw ring muxer when mcbp is disabled.
Signed-off-by: Jiadong Zhu
---
drive
From: Jiadong Zhu
The parameter amdgpu_mcbp shall have priority against the default value
calculated from the chip version.
User could disable mcbp by setting the parameter mcbp as zero.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +
1 file changed, 5
From: Jiadong Zhu
The driver's CSA buffer is shared by all the ibs. When the high priority ib
is submitted after the preempted ib, CP overrides the ib_completion_status
as completed in the csa buffer. After that the preempted ib is resubmitted,
CP would clear some locals stored for ib resume when
From: Jiadong Zhu
Gfx9 is using software rings which would trigger mcbp in some cases.
Thus the parameter amdgpu_mcbp shall be enabled by default.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Jiadong Zhu
Only low priority rings are using chunks to save the offset.
Bypass the mark offset callings from high priority rings.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Jiadong Zhu
When the preempted IB frame resubmitted to cp, we need to modify the frame
data including:
1. set PRE_RESUME 1 in CONTEXT_CONTROL.
2. use meta data(DE and CE) read from CSA in WRITE_DATA.
Add functions to save the location the first time IBs emitted and callback
to patch the pa
From: Jiadong Zhu
Patch the packages including CONTEXT_CONTROL and WRITE_DATA for gfx9
during the resubmission scenario.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 80 +++
1 file changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/amd/amd
From: Jiadong Zhu
It is firmware requirement to set gds_backup_addrlo and gds_backup_addrhi
of DE meta both zero if no gds partition is allocated for the frame.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 -
1 file changed, 8 insertions(+), 5 deletions
From: Jiadong Zhu
When MEC executes unmap_queue for mid command buffer preemption, it will
kick the write pointer of the gfx ring, set CP_VMID_PREEMPT to trigger the
preemption and wait for CP_VMID_PREEMPT becomes zero after the preemption
done. There is a race condition that PFP may excute the r
From: Jiadong Zhu
lkp robot reported missing-prototypes and unused-but-set-variable warnings on
some functions of amdgpu_mcbp_mux.c. Make them static and remove the unused
variable.
Reported-by: kernel test robot
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 8
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: jiadozhu
This is a standalone test case used for software mcbp on gfx9.
Build and open two consoles to run:
build/bin/vkpreemption s gfx=draws:100,priority:high,delay:0
build/bin/vkpreemption c gfx=draws:100,priority:low,delay:0
The result is printed on the console of the server si
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: Jiadong Zhu
Using the drm scheduler, the software rings' scheduling threads with different
priorities have the same opportunity to get the spinlock and copy its packages
into the real ring. Though preemption may happen for the low priority ring, it
will catch up with the high priority ring
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
The function amdgpu_fence_count_emitted used in work_hander should not call
amdgpu_fence_process which must be used in irq handler.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drive
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
The current position calulated in gfx_v9_0_ring_emit_patch_cond_exec
underflows when the wptr is divisible by ring->buf_mask + 1.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
Signed-off-by: Jiadong.Zhu
--
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for soft
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the
From: "Jiadong.Zhu"
The software ring is created to support priority
context while there is only one hardware queue
for gfx.
Every software rings has its fence driver and could
be used as an ordinary ring for the gpu_scheduler.
Multiple software rings are binded to a real ring
wit
From: "Jiadong.Zhu"
Trigger MCBP according to the priroty of the
software rings and the hw fence signaling
condition.
The muxer records some lastest locations from the
software ring which is used to resubmit packages
in preemption scenarios.
v2: update comment style
Signed-off-by: J
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9.
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
v2: restyle code not to use ternary operator.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/
From: "Jiadong.Zhu"
The software ring is created to support priority
context while there is only one hardware queue
for gfx.
Every software rings has its fence driver and could
be used as an ordinary ring for the gpu_scheduler.
Multiple software rings are binded to a real ring
wit
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks
on gfx9.
The software ring could be tested by debugfs_test_ib
case.
v2: set sw_ring 2 to enable software ring by default.
v3: remove the parameter for software ring enablement.
Signed-off-by: Jiadong.Zhu
---
drive
From: "Jiadong.Zhu"
1. Use unmap_queue package to trigger preemption on gfx9
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
d
From: "Jiadong.Zhu"
1. Use unmap_queue package to trigger preemption on gfx9
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/
From: "Jiadong.Zhu"
Set register to enable mcbp according to amdgpu_mcbp.
Add sdma preempt_ib function used for debugfs test.
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 53 ++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma
From: "Jiadong.Zhu"
Set register to enable mcbp according to amdgpu_mcbp.
Add sdma preempt_ib function used for debugfs test.
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 53 ++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma
From: "Jiadong.Zhu"
1. Use unmap_queue package to trigger preemption on gfx9
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/
From: "Jiadong.Zhu"
Set register to enable mcbp according to amdgpu_mcbp.
Add sdma preempt_ib function used for debugfs test.
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 53 ++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma
From: "Jiadong.Zhu"
Dma_fence_signal returning non-zero indicates
that the fence is signaled and put somewhere else.
Skip dma_fence_put to make the fence refcount correct.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
1 file changed, 2 insert
From: "Jiadong.Zhu"
1. Use unmap_queue package to trigger preemption on gfx9
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/
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