RE: [PATCH 3/5] drm/amdgpu: Prevent race between late signaled fences and GPU reset.

Hi, Is this a preventive fix or you found errors/oops/hangs? If you had found errors/oops/hangs, can you please share the details? BR, Chandan V N >On 2022-06-21 03:25, Christian König wrote: >> Am 21.06.22 um 00:03 schrieb Andrey Grodzovsky: >>> Problem: >>> After we start handling timed out j

RE: [PATCH] amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE doing nothing for DCN20+

Hi Alex, I think this was pushed earlier by Harry. Not sure why it did not get merged. https://www.spinics.net/lists/stable/msg543116.html has the history. BR, Chandan V N >Applied. Thanks! > >Alex > >On Wed, Jun 15, 2022 at 9:21 PM Joshua Ashton wrote: >> >> For DCN20 and above, the code that

RE: [PATCH 20/23] drm/amd/display: Disables dynamic memory clock switching in games

Hi, Can you please elaborate on why dynamic memory clock switching can affect Game performance? BR, Chandan V N >On 2022-06-10 22:52, Hamza Mahfooz wrote: >> From: Harry VanZyllDeJong >> >> [WHY] >> Game performace may be affected if dynamic memory clock switching is >> enabled while playin

RE: [PATCH] drm/amdgpu/display: Remove unnecessary typecasts and fix build issues

Hi, >> >> >> On 2022-06-07 05:40, Chandan Vurdigere Nataraj wrote: >>> [Why] >>> Getting below errors: >>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5: >>> error: implicit conversion from enumeration type 'enum >>> scan_direction_class' to different enumerat

RE: [PATCH AUTOSEL 5.17 13/23] drm/amd/display: undo clearing of z10 related function pointers

Hi, Is S0i3 verified for DCN 3.1.6 with this? BR, Chandan V N >From: Eric Yang > >[ Upstream commit 9b9bd3f640640f94272a461b2dfe558f91b322c5 ] > > [Why] >Z10 and S0i3 have some shared path. Previous code clean up , incorrectly >removed these pointers, which breaks s0i3 restore > > [How] >Do no

RE: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc

Hi, Changes are not needed in " drivers/gpu/drm/amd/display/Kconfig" ?? Also, is this change validated on Chrome? BR, Chandan V N >What about arm? > >-Original Message- >From: amd-gfx On Behalf Of Rodrigo >Siqueira Jordao >Sent: 2022年5月7日 1:13 >To: Alex Deucher ; Hung, Alex ; >Wang, C

RE: [PATCH 14/17] drm/amd/display: add shared helpers to update psr config fields to power module

Hi >[why] >Currently the amdgpu DM psr configuration parameters are hardcoded before >feeding into the DC helper to setup PSR. We would define a helper >which is to >calculate parts of the psr config fields to avoid hard-coding. > >[how] >To make helper shareable, declare and define the helper

RE: [PATCH 05/17] drm/amd/display: revise Start/End SDP data

Hi, Why not set "vsc_packet_rev2" when "stream->link->psr_settings.psr_version == DC_PSR_VERSION_1"? This would be safer for future PSR versions also. BR, Chandan V N >[why & how] >We need to implement the VSC packet rev4 that is required by PSRSU. > >Follow the eDP 1.5 spec pg. 257 > >Signed-

RE: [PATCH 03/17] drm/amd/display: combine dirty rectangles in DMUB FW

Hi, Why is the DC_MAX_DIRTY_RECTS set to 3? What causes this limitation? >[why] >In PSR-SU design, the DMUB FW handles the combination of multiple dirty >rectangles. > >[how] >- create DC dmub update dirty rectangle helper which sends the > dirty rectangles per pipe from DC to DMUB, and DMUB

RE: [PATCH v2] drm/amdgpu: fix that issue that the number of the crtc of the 3250c is not correct

>Hi Chandan, > >This issue we found on the Zork project which uses the kernel 5.4 on. So I >just implemented it on kernel 5.4. >For finding out which is 3250c, I referenced the function which is implemented >from another function. >Below is the part where I found it. > >drivers/gpu/drm/amd/amdgpu

RE: [PATCH v2] drm/amdgpu: fix that issue that the number of the crtc of the 3250c is not correct

Hi Ryan, Is this change applicable on a specific kernel version? On latest I see IP DISCOVERY based impl for CHIP_RAVEN. >[Why] >External displays take priority over internal display when there are fewer >display controllers than displays. > > [How] >The root cause is because of that number of

RE: [PATCH] drm/amd/display: Fix by adding FPU protection for dcn30_internal_validate_bw

Hi Paul, >Am 29.03.22 um 10:29 schrieb CHANDAN VURDIGERE NATARAJ: > >Is it common to spell your name all uppercase? If not, please use Chandan >nVurdigere Nataraj. > >> [WHY] > >The [] already emphasize the word, so Why could be used. > >> Below general protection fault observed when WebGL Aquari