On Thu, 2025-08-07 at 16:34 -0400, Harry Wentland wrote:
>
>
> On 2025-08-07 15:12, Harry Wentland wrote:
> > On 2025-07-23 11:58, Timur Kristóf wrote:
> > > Analog displays typically have a DDC connection which can be
> > > used by the GPU to read EDID. This co
Harry Wentland ezt írta (időpont: 2025. aug. 6.,
Sze 16:56):
> On 2025-07-23 11:57, Timur Kristóf wrote:
> > Previously, DC determined the DRM connector type based on the
> > signal type, which becomes problematic when a connector may
> > support different signal
On Mon, 2025-08-04 at 20:59 +0200, Christian König wrote:
> On 04.08.25 19:45, Alex Deucher wrote:
> > On Mon, Aug 4, 2025 at 12:00 PM Timur Kristóf
> > wrote:
> > >
> > > On Mon, 2025-08-04 at 11:20 -0400, Alex Deucher wrote:
> > > > On Mon, Aug 4,
On Mon, 2025-08-04 at 13:45 -0400, Alex Deucher wrote:
> On Mon, Aug 4, 2025 at 12:00 PM Timur Kristóf
> wrote:
> >
> > On Mon, 2025-08-04 at 11:20 -0400, Alex Deucher wrote:
> > > On Mon, Aug 4, 2025 at 9:58 AM Timur Kristóf
> > > wrote:
> > >
On Mon, 2025-08-04 at 11:56 -0400, Alex Deucher wrote:
> On Thu, Jul 31, 2025 at 5:58 AM Timur Kristóf
> wrote:
> >
> > Adjust the nominal (and performance) clocks for DCE 8-10,
> > and set them to 625 MHz, which is the value used by the legacy
> > display code in
On Mon, 2025-08-04 at 11:32 -0400, Alex Deucher wrote:
> On Mon, Aug 4, 2025 at 9:42 AM Timur Kristóf
> wrote:
> >
> > The si_upload_smc_data function uses si_write_smc_soft_register
> > to set some register values in the SMC, and expects the result
> > to
On Mon, 2025-08-04 at 11:24 -0400, Alex Deucher wrote:
> On Mon, Aug 4, 2025 at 10:18 AM Timur Kristóf
> wrote:
> >
> > Backport of the same commit to amdgpu.
> > This commit fixes some instability on Tahiti.
>
> Have you tested this with radeon?
>
> Ale
On Mon, 2025-08-04 at 11:24 -0400, Alex Deucher wrote:
> On Mon, Aug 4, 2025 at 9:58 AM Timur Kristóf
> wrote:
> >
> > This commit fixes some instability on Tahiti.
> >
> > Sometimes UVD initialization would fail when using DC.
> > I suspect this is becaus
On Mon, 2025-08-04 at 11:20 -0400, Alex Deucher wrote:
> On Mon, Aug 4, 2025 at 9:58 AM Timur Kristóf
> wrote:
> >
> > Unlike later versions, UVD 3 has firmware validation.
> > For this to work, the UVD should be powered up correctly.
> >
> > When DPM is
x27;t have that for old GPUs, so
ad-hoc fixes become necessary.
Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/
upport (v4)")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 31 +-
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 33b9d4beec84..e9f0
Fixes: a9e61410921b ("drm/radeon/kms: add dpm support for SI (v7)")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/radeon/si_dpm.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon
Backport of the same commit to amdgpu.
This commit fixes some instability on Tahiti.
Fixes: a9e61410921b ("drm/radeon/kms: add dpm support for SI (v7)")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/radeon/si_dpm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
di
("drm amdgpu: SI UVD v3_1 (v2)")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 5dbaebb592b3..9ad0
This commit fixes some instability on Tahiti.
Sometimes UVD initialization would fail when using DC.
I suspect this is because DC doesn't immediately turn on the
display clock, so it changes how DPM behaves.
Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Signed-off-by
d-hoc fixes. This fixes different flickering
issues that I observed on Oland, Tahiti and Pitcairn.
Timur Kristóf (6):
drm/amdgpu: Power up UVD 3 for FW validation
drm/amd/pm: Disable ULV even if unsupported
drm/radeon: Disable ULV even if unsupported
drm/amd/pm: Fix si_upload_smc_data
On Sun, 2025-08-03 at 12:26 -0400, Alexandre Demers wrote:
> On Fri, Aug 1, 2025 at 6:02 PM Timur Kristóf
> wrote:
> >
> > Hi Alexandre,
> >
> > With regards to the coding style. I already replied to your other
> > thread about it, let's have that con
On Sun, 2025-08-03 at 12:10 -0400, Alexandre Demers wrote:
> Hi Timur,
>
> I agree with you about the coding style (the prefix), it was more of
> a general comment since the style is inconsistent with some other
> parts in the DC code.
>
> If the code applies to any DCE version (even though it is
DCE 6 was not advertised as being able to support VRR,
so let's mark it as unsupported for now.
The VRR implementation in amdgpu_dm depends on the VUPDATE
interrupt which is not registered for DCE 6.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.
The VUPDATE interrupt isn't registered on DCE 6, so don't try
to use that.
This fixes a page flip timeout after sleep/resume on DCE 6.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ---
.../amd/display/amdgpu_dm/amdgpu_dm_crtc
It already didn't work on DCE 8,
so there is no reason to assume it would on DCE 6.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/d
idn't work
on DCE 8, and even if it did I have no means to test it.
Timur Kristóf (3):
drm/amd/display: Disable fastboot on DCE 6 too.
drm/amd/display: Disable VRR on DCE 6
drm/amd/display: Don't use non-registered VUPDATE on DCE 6
.../gpu/drm/amd/display/amdgpu
above GPUs, at the following settings:
* 4K 60 Hz
* 1080p 60 Hz
* 1080p 144 Hz
Signed-off-by: Timur Kristóf
---
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 21 ++-
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60
rred engine type is still going to be digital. So, for DVI-I
>> to work, we need to make sure the pre-existing link encoder can
>> also work with analog signals.
>>
>> Signed-off-by: Timur Kristóf
>> ---
>> .../drm/amd/display/dc/dce/dce_link_encoder.c | 100 +++
an analog stream, and it is beneficial to split them from
>> digital stream encoders in the code to make sure they don't
>> accidentally write any DIG* registers.
>>
>> Signed-off-by: Timur Kristóf
>> ---
>> .../drm/amd/display/dc/dce/dce_stream_encoder.c
On Fri, 2025-08-01 at 10:55 -0400, Harry Wentland wrote:
>
>
> On 2025-08-01 04:39, Timur Kristóf wrote:
> > On Fri, 2025-08-01 at 03:19 -0400, Alexandre Demers wrote:
> > > > On 2025-07-30 13:08, Timur Kristóf wrote:
> > > > > On Wed, 2025-
On Fri, 2025-08-01 at 03:19 -0400, Alexandre Demers wrote:
> > On 2025-07-30 13:08, Timur Kristóf wrote:
> > > On Wed, 2025-07-30 at 10:34 -0400, Harry Wentland wrote:
> > > >
> > > >
> > > > On 2025-07-30 04:19, Timur Kristóf wrote:
> >
dce110_fill_display_configs is shared between DCE 6-11, and
finding the first CRTC and its line time is relevant to DCE 6 too.
Move the code to find it from DCE 11 specific code.
Signed-off-by: Timur Kristóf
---
.../dc/clk_mgr/dce110/dce110_clk_mgr.c| 30 ---
1 file
ors, don't litter the logs.
Fixes: 60df5628144b ("drm/amd/display: handle invalid connector indices")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 5 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 ++-
2 files cha
On some GPUs the VBIOS just doesn't have encoder caps,
or maybe not for every encoder.
This isn't really a problem and it's handled well,
so let's not litter the logs with it.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 8 ---
fixes set_pixel_clock_v3 by dividing the fractional
feedback divider passed to the function by 10.
Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +-
1 file changed, 1 insertion
Also needed by DCE 6.
This way the code that gathers this info can be shared between
different DCE versions and doesn't have to be repeated.
Signed-off-by: Timur Kristóf
---
.../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c| 2 --
.../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_
that and also adds a check to make sure
not to exceed the maximum DCE 8-10 display clock.
Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
Signed-off-by: Timur Kristóf
x
---
.../d
m/amd/display: dc/clk_mgr: add support for SI parts
(v2)")
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.
logs with them.
Finally, there is also a fix for set_pixel_clock_v3 which
works slightly differently than the other versions.
Timur Kristóf (7):
drm/amd/display: Don't overclock DCE 6 by 15%
drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
drm/amd/display: Find first CR
On Wed, 2025-07-30 at 13:29 -0400, Harry Wentland wrote:
>
>
> On 2025-07-30 13:03, Timur Kristóf wrote:
> > On Wed, 2025-07-30 at 10:30 -0400, Harry Wentland wrote:
> > >
> > >
> > > On 2025-07-30 03:40, Timur Kristóf wrote:
> > > > O
On Wed, 2025-07-30 at 12:29 -0400, Harry Wentland wrote:
>
>
> The series looks good to me.
>
> Patches 2-20 are
> Reviewed-by: Harry Wentland
>
> Patch 1 is probably good, just waiting for feedback on my comments.
>
> Though I would like to send this through our weekly testing cycle
> before
On Wed, 2025-07-30 at 10:34 -0400, Harry Wentland wrote:
>
>
> On 2025-07-30 04:19, Timur Kristóf wrote:
> > On Tue, 2025-07-29 at 14:21 -0400, Harry Wentland wrote:
> > >
> > >
> > > On 2025-07-23 11:58, Timur Kristóf wrote:
> > > > Featur
On Wed, 2025-07-30 at 10:30 -0400, Harry Wentland wrote:
>
>
> On 2025-07-30 03:40, Timur Kristóf wrote:
> > On Tue, 2025-07-29 at 14:03 -0400, Harry Wentland wrote:
> > >
> > >
> > > On 2025-07-23 11:57, Timur Kristóf wrote:
> > > > Pre
On Tue, 2025-07-29 at 14:21 -0400, Harry Wentland wrote:
>
>
> On 2025-07-23 11:58, Timur Kristóf wrote:
> > Features like stereo sync and audio are not supported by RGB
> > signals, so don't try to use them.
> >
>
> Where does it say that?
>
> Har
On Tue, 2025-07-29 at 14:06 -0400, Harry Wentland wrote:
>
>
> On 2025-07-23 11:57, Timur Kristóf wrote:
> > We are going to support analog encoders as well, not just digital,
> > so we need to make space for them in various arrays.
> >
> > Signed-off-by: Timur
On Tue, 2025-07-29 at 14:03 -0400, Harry Wentland wrote:
>
>
> On 2025-07-23 11:57, Timur Kristóf wrote:
> > Previously, DC determined the DRM connector type based on the
> > signal type, which becomes problematic when a connector may
> > support different
>
> Thanks!
>
> Alex
>
> On Tue, Jul 22, 2025 at 12:23 PM Timur Kristóf
> wrote:
> >
> > Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only
> > be used for DP. Make sure to initialize the correct amount of PLLs
> > in DC for these DCE
let's wait for ASDN to be updated.
>
Yes, it indeed looks like that patch addresses the same problem.
>
> On 7/24/25 16:32, Rodrigo Siqueira wrote:
> > On 010/22, Timur Kristóf wrote:
> >> After refactoring the DSC capability calculation, the
> >> get_min_
On Thu, 2025-07-24 at 16:40 -0600, Rodrigo Siqueira wrote:
> On 07/22, Timur Kristóf wrote:
> > dc_clk_mgr_create accidentally overwrites the dce60_clk_mgr
> > with the dce_clk_mgr, causing incorrect behaviour on DCE6.
>
> Could you ellaborate on what do you mean by inc
Now that DC supports analog connectors, there is nothing stopping
us from using it by default on Bonaire.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm
ch we already do in amdgpu_dm_connector_get_modes.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++
.../drm/amd/display/dc/link/link_detection.c | 43 +++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdg
ating systems as well as the
legacy display code path in amdgpu.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +++
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/dr
This will be reused by DAC load detection.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
b/drivers/gpu/drm/amd/display/dc
output to the DAC.
Signed-off-by: Timur Kristóf
---
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 75 ++-
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dce110
DAC_LoadDetection can be used to determine whether something
is connected to an analog connector, primarily when the connected
display doesn't have an EDID.
As a reference, I used the following function:
amdgpu_atombios_encoder_dac_load_detect
Signed-off-by: Timur Kristóf
---
.../gpu/dr
es do this so we can't rely on
this feature, therefore we need to poll DVI-I connectors as well.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 60 ++-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 8 +++
2 files changed, 66 insert
RGB signal, search for analog stream encoders.
The actual DCE analog stream encoder support is going to be
added in a subsequent commit.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 8 ++
.../drm/amd/display/dc/inc/hw/link_encoder.h | 2 ++
drivers/gpu
The BIOS uses this register to write the results of the
DAC_LoadDetection command, so we'll need to read this
in order to make DAC load detection work.
As a reference, I used the mmBIOS_SCRATCH_0 definition from
the amdgpu legacy display code.
Signed-off-by: Timur Kristóf
---
drivers/gp
following functions:
amdgpu_connector_vga_detect
amdgpu_display_ddc_probe
DAC load detection will be implemented in a separate commit.
Signed-off-by: Timur Kristóf
---
.../amd/display/dc/link/hwss/link_hwss_dio.c | 16 ++--
.../drm/amd/display/dc/link/link_detection.c | 80
, which allows both digital and analog signals:
The DC code base only allows 1 encoder per connector, and the
preferred engine type is still going to be digital. So, for DVI-I
to work, we need to make sure the pre-existing link encoder can
also work with analog signals.
Signed-off-by: Timur Kristóf
We will use this for validating the pixel clock when
an analog monitor is connected to VGA or DVI-I connectors.
Reference in the legacy code:
amdgpu_connector_vga_mode_valid
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 ++
drivers/gpu/drm/amd
We are going to support analog encoders as well, not just digital,
so we need to make space for them in various arrays.
Signed-off-by: Timur Kristóf
---
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 4 ++--
.../gpu/drm/amd/display/dc/inc/core_types.h | 8 +++
.../gpu/drm/amd/display
Features like stereo sync and audio are not supported by RGB
signals, so don't try to use them.
Also add a dc_is_rgb_signal similar to other dc_is_*_signal.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c | 3 ++-
drivers/gpu/drm/amd/display/dc
encoder to do, making them basically a no-op.
That being said, we still need some kind of stream encoder to
represent an analog stream, and it is beneficial to split them from
digital stream encoders in the code to make sure they don't
accidentally write any DIG* registers.
Signed-off-by:
VGA connectors don't have HPD (hotplug detection), so don't
touch any HPD related registers for VGA.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/a
The SelectCRTC_Source command will be used to change which CRTC
should be connected to which encoder.
To implement this, I used the legacy display code as reference:
amdgpu_atombios_encoder_set_crtc_source
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/dc/bios/bios_parser.c | 14
The BIOS parser already supports calling the DAC1EncoderControl
function from the VBIOS, but it was not exposed anywhere.
This commit enables the codebase to use encoder_control()
when the encoder engine is one of the DACs.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/dc/bios
ort, which is useful for old displays and adapters.
Please let me know what you think.
Timur Kristóf (20):
drm/amd/display: Determine DRM connector type more accurately
drm/amd/display: Add analog bit to edid_caps
drm/amd/display: Introduce MAX_LINK_ENCODERS
drm/amd/dis
The new analog bit will be used with DVI-I connectors.
DVI-I connectors can connect to both digital and analog monitors
and this bit will help distinguish between those.
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 +
drivers/gpu/drm/amd
and DVI-I connectors.
A subsequent commit will enable polling for these connectors.
Signed-off-by: Timur Kristóf
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm
use a different
clock source for DFS.
The following functions were used as reference from the old
radeon driver implementation of DCE 6.x:
- radeon_atom_pick_pll
- atombios_crtc_set_disp_eng_pll
Signed-off-by: Timur Kristóf
---
.../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 5 +++
.../dc
dc_clk_mgr_create accidentally overwrites the dce60_clk_mgr
with the dce_clk_mgr, causing incorrect behaviour on DCE6.
Fix it by removing the extra dce_clk_mgr_construct.
Fixes: 62eab49faae7 ("drm/amd/display: hide VGH asic specific structs")
Signed-off-by: Timur Kristóf
---
drivers/g
This series fixes some regressions in DC, mainly on DCE6-8.
There is a fix for a recent regression caused by refactoring
the DSC cap calculation that affects DCE8-10, as well as
some fixes related to clock sources in DCE 6.
Timur Kristóf (3):
drm/amd/display: Fix refactored DSC cap
Oland (DCE 6) and Fiji (DCE 10).
This commit fixes it by returning zero instead.
Fixes: 4909b8b3846c ("drm/amd/display: Refactor DSC cap calculations")
Signed-off-by: Timur Kristóf
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 17 +
1 file changed, 9 insertions(
Hi André,
Sorry for the late reply - we've been discussing all of this on a
different, long email thread.
Alex & Christian - do you think it's OK to include André on that
thread?
André - in a nutshell, I was using a Mesa patch that intentionally
breaks NGG culling:
https://gitlab.freedesktop.org
On Tue, 2023-07-25 at 19:00 +0200, Michel Dänzer wrote:
> On 7/25/23 17:05, Marek Olšák wrote:
> > On Tue, Jul 25, 2023 at 4:03 AM Michel Dänzer
> > wrote:
> > > On 7/25/23 04:55, André Almeida wrote:
> > > > Hi everyone,
> > > >
> > > > It's not clear what we should do about non-robust OpenGL ap
Hi Felix,
On Wed, 2023-05-03 at 11:08 -0400, Felix Kuehling wrote:
> That's the worst-case scenario where you're debugging HW or FW
> issues.
> Those should be pretty rare post-bringup. But are there hangs caused
> by
> user mode driver or application bugs that are easier to debug and
> probabl
On Tue, 2023-05-02 at 09:45 -0400, Alex Deucher wrote:
> On Tue, May 2, 2023 at 9:35 AM Timur Kristóf
> wrote:
> >
> > Hi,
> >
> > On Tue, 2023-05-02 at 13:14 +0200, Christian König wrote:
> > > >
> > > > Christian König ezt
Hi,
On Tue, 2023-05-02 at 13:14 +0200, Christian König wrote:
> >
> > Christian König ezt írta (időpont: 2023.
> > máj. 2., Ke 9:59):
> >
> > > Am 02.05.23 um 03:26 schrieb André Almeida:
> > > > Em 01/05/2023 16:24, Alex Deucher escreveu:
> > > >> On Mon, May 1, 2023 at 2:58 PM André Almeid
Hi Christian,
Christian König ezt írta (időpont: 2023. máj.
2., Ke 9:59):
> Am 02.05.23 um 03:26 schrieb André Almeida:
> > Em 01/05/2023 16:24, Alex Deucher escreveu:
> >> On Mon, May 1, 2023 at 2:58 PM André Almeida
> >> wrote:
> >>>
> >>> I know that devcoredump is also used for this kind of
Bas Nieuwenhuizen ezt írta (időpont: 2023. ápr.
11., Ke 10:25):
> On Tue, Apr 11, 2023 at 10:10 AM Christian König
> wrote:
> >
> > Am 09.04.23 um 20:59 schrieb Bas Nieuwenhuizen:
> > > We need to introduce a new version of the info struct because
> > > libdrm_amdgpu forgot any versioning info i
Christian König ezt írta (időpont: 2023. ápr.
11., Ke 11:23):
> Am 11.04.23 um 11:06 schrieb Timur Kristóf:
>
>
>
> Bas Nieuwenhuizen ezt írta (időpont: 2023. ápr.
> 11., Ke 10:25):
>
>> On Tue, Apr 11, 2023 at 10:10 AM Christian König
>> wrote:
>>
Christian König ezt írta (időpont: 2023.
ápr. 9., Vas 17:38):
> Am 09.04.23 um 17:32 schrieb Bas Nieuwenhuizen:
> > On Sun, Apr 9, 2023 at 5:30 PM Christian König
> > wrote:
> >> Am 09.04.23 um 16:44 schrieb Bas Nieuwenhuizen:
> >>> We need to introduce a new version of the info struct because
>
with that.
>
> Thanks,
> Christian.
>
> Am 18.11.22 um 16:36 schrieb Timur Kristóf:
> > Can you guys please push this into the next 6.1 RC? This solves a
> > significant issue with gang submit.
> >
> > On Fri, 2022-11-18 at 16:30 +0100, Christian König wrote:
> &g
istian König
> Tested-by: Timur Kristóf
> Acked-by: Timur Kristóf
> Fixes: 68ce8b242242 ("drm/amdgpu: add gang submit backend v2")
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/g
I can confirm this patch solves an issue with gang submit.
It removes the necessity to sort IBs by IP type in user space.
Now only the IP type of the last IB matters, as was intended.
Tested-by: Timur Kristóf
Acked-by: Timur Kristóf
On Tue, 2022-11-15 at 10:43 +0100, Christian König wrote
On Sat, 2020-02-29 at 14:46 -0500, Nicolas Dufresne wrote:
> >
> > 1. I think we should completely disable running the CI on MRs which
> > are
> > marked WIP. Speaking from personal experience, I usually make a lot
> > of
> > changes to my MRs before they are merged, so it is a waste of CI
> > res
On Fri, 2020-02-28 at 10:43 +, Daniel Stone wrote:
> On Fri, 28 Feb 2020 at 10:06, Erik Faye-Lund
> wrote:
> > On Fri, 2020-02-28 at 11:40 +0200, Lionel Landwerlin wrote:
> > > Yeah, changes on vulkan drivers or backend compilers should be
> > > fairly
> > > sandboxed.
> > >
> > > We also hav
84 matches
Mail list logo
