[PATCH] drm/amdgpu: avoid clearing freed bo with sdma in gpu reset

ished before sdma ip suspend. HOW: here is to add mutex_lock to wait to avoid using sdma during gpu reset. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gp

[PATCH 2/2] drm/amd/powerplay: avoid using pm_en before it is initialized revised

to pp_set_asic_baco_state (pm_en) pm_en is used in the above two cases while it has not yet been initialized So avoid using pm_en in the above two functions for V320 passthrough. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 -- 1 file changed, 4 insertions(+), 2 deleti

[PATCH 1/2] Revert "drm/amd/powerplay: avoid using pm_en before it is initialized"

This reverts commit 764a21cb085b8d7d754b5d74e2ecc6adc064e3e7. The commit being reverted changed the wrong place, it should have changed in func get_asic_baco_capability. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 +-- 1 file changed, 1 insertion(+), 2

[PATCH 1/2] Revert "drm/amd/powerplay: avoid using pm_en before it is initialized"

This reverts commit 764a21cb085b8d7d754b5d74e2ecc6adc064e3e7. The commit being reverted changed the wrong place, it should have changed in func get_asic_baco_capability. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 +-- 1 file changed, 1 insertion(+), 2

[PATCH 2/2] drm/amd/powerplay: avoid using pm_en before it is initialized revised

hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. this is to avoid using pm_en in pp_get_asic_baco_capability Signed-off-by: Tiecheng Zhou Signed-

[PATCH] drm/amd/powerplay: avoid using pm_en before it is initialized 2nd

hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. this is a second patch that avoid using pm_en in pp_get_asic_baco_capability Signed-off-by: Ti

[PATCH] drm/amd/powerplay: avoid using pm_en before it is initialized

hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. so avoid using pm_en in pp_get_asic_baco_capability. Signed-off-by: Tiecheng Zhou Signed-

[PATCH] drm/amd/powerplay: determine pm_en at amd_powerplay_create

Need to determine pm_en at amd_powerplay_create of early_init stage. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 +++ drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH] drm/amdgpu/sriov: skip programing some regs with new L1 policy

GCMC_VM_SYSTEM_APERTURE_LOW_ADDR MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR MMMC_VM_SYSTEM_APERTURE_LOW_ADDR HDP_NONSURFACE_BASE HDP_NONSURFACE_BASE_HI GCMC_VM_AGP_TOP GCMC_VM_AGP_BOT GCMC_VM_AGP_BASE Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 55 +++- drivers/gpu/drm/amd

[PATCH] drm/amdgpu/sriov: workaround on rev_id for Navi12 under sriov

guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0, as a consequence, the rev_id and external_rev_id are wrong. workaround it by hardcoding the rev_id to 0, which is the default value. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++ 1 file changed, 2 insertions

[PATCH] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. v2: it should not hurt baremetal, generalize it for both sriov and baremetal Signed-off-by: Emily Deng Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0

[PATCH] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. Signed-off-by: Emily Deng Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm

[PATCH] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. Signed-off-by: Emily Deng Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm

[PATCH] drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence

The kiq ring and the very first compute ring may fail occasionally if they are tested directly following kiq_kcq_enable. Insert the gfx ring test before kiq ring test to delay the kiq and kcq ring tests will fix the issue. Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[PATCH] drm/amdgpu: bypass RLC init under sriov for Tonga

SWDEV-173384: vm-mix reboot (4 VMs) fail on Tonga under sriov Phenomena: there is compute_1.3.1 ring test fail on one VM when it starts to do hw_init after it is rebooted Root cause: RLC will go wrong in soft_reset under sriov Workaround: init RLC csb, and skip RLC stop, reset, start

[PATCH] drm/amdgpu/sriov: sriov won't support gfx off

Signed-off-by: Tiecheng Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 790fd54..e67ab25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b