On 6/29/2023 5:29 PM, Philip Yang wrote:
If the SVM range has no GPU access or access-in-place attribute,
Just a nit-pick. Shouldn't be no GPU access nor access-in-place?
validate and map to GPU should skip the range.
Add NULL pointer check if find_first_bit(ctx->bitmap, MAX_GPU_INSTANCE)
retu
[AMD Official Use Only - General]
CC: Rajneesh
> -Original Message-
> From: Sierra Guiza, Alejandro (Alex)
> Sent: Thursday, June 15, 2023 5:55 PM
> To: amd-gfx@lists.freedesktop.org; Kuehling, Felix
> Cc: Yat Sin, David ; Sierra Guiza, Alejandro (Alex)
>
> Subjec
On 7/18/2022 3:32 PM, Andrew Morton wrote:
On Mon, 18 Jul 2022 12:56:29 +0200 David Hildenbrand wrote:
/*
* Try to move out any movable page before pinning the range.
*/
@@ -1919,7 +1948,8 @@ static long check_and_migrate_movable_pages(unsign
On 7/14/2022 9:11 PM, Alistair Popple wrote:
Currently any attempts to pin a device coherent page will fail. This is
because device coherent pages need to be managed by a device driver, and
pinning them would prevent a driver from migrating them off the device.
However this is no reason to fai
On 6/28/2022 5:42 AM, David Hildenbrand wrote:
On 28.06.22 02:14, Alex Sierra wrote:
With DEVICE_COHERENT, we'll soon have vm_normal_pages() return
device-managed anonymous pages that are not LRU pages. Although they
behave like normal pages for purposes of mapping in CPU page, and for
COW. Th
On 6/23/2022 1:21 PM, David Hildenbrand wrote:
On 23.06.22 20:20, Sierra Guiza, Alejandro (Alex) wrote:
On 6/23/2022 2:57 AM, David Hildenbrand wrote:
On 23.06.22 01:16, Sierra Guiza, Alejandro (Alex) wrote:
On 6/21/2022 11:16 AM, David Hildenbrand wrote:
On 21.06.22 18:08, Sierra Guiza
On 6/23/2022 2:57 AM, David Hildenbrand wrote:
On 23.06.22 01:16, Sierra Guiza, Alejandro (Alex) wrote:
On 6/21/2022 11:16 AM, David Hildenbrand wrote:
On 21.06.22 18:08, Sierra Guiza, Alejandro (Alex) wrote:
On 6/21/2022 7:25 AM, David Hildenbrand wrote:
On 21.06.22 13:55, Alistair Popple
On 6/21/2022 11:16 AM, David Hildenbrand wrote:
On 21.06.22 18:08, Sierra Guiza, Alejandro (Alex) wrote:
On 6/21/2022 7:25 AM, David Hildenbrand wrote:
On 21.06.22 13:55, Alistair Popple wrote:
David Hildenbrand writes:
On 21.06.22 13:25, Felix Kuehling wrote:
Am 6/17/22 um 23:19
On 6/21/2022 7:16 PM, Alistair Popple wrote:
David Hildenbrand writes:
On 21.06.22 18:08, Sierra Guiza, Alejandro (Alex) wrote:
On 6/21/2022 7:25 AM, David Hildenbrand wrote:
On 21.06.22 13:55, Alistair Popple wrote:
David Hildenbrand writes:
On 21.06.22 13:25, Felix Kuehling wrote
On 6/21/2022 7:25 AM, David Hildenbrand wrote:
On 21.06.22 13:55, Alistair Popple wrote:
David Hildenbrand writes:
On 21.06.22 13:25, Felix Kuehling wrote:
Am 6/17/22 um 23:19 schrieb David Hildenbrand:
On 17.06.22 21:27, Sierra Guiza, Alejandro (Alex) wrote:
On 6/17/2022 12:33 PM
On 6/17/2022 12:33 PM, David Hildenbrand wrote:
On 17.06.22 19:20, Sierra Guiza, Alejandro (Alex) wrote:
On 6/17/2022 4:40 AM, David Hildenbrand wrote:
On 31.05.22 22:00, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms
On 6/17/2022 4:40 AM, David Hildenbrand wrote:
On 31.05.22 22:00, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a process can be migrated to such memory. Howe
On 5/31/2022 12:31 PM, Andrew Morton wrote:
On Tue, 31 May 2022 10:56:23 -0500 Alex Sierra wrote:
new ioctl cmd added to query zone device type. This will be
used once the test_hmm adds zone device coherent type.
@@ -1026,6 +1027,15 @@ static int dmirror_snapshot(struct dmirror *dmirror,
On 5/24/2022 11:11 PM, Alistair Popple wrote:
Alex Sierra writes:
With DEVICE_COHERENT, we'll soon have vm_normal_pages() return
device-managed anonymous pages that are not LRU pages. Although they
behave like normal pages for purposes of mapping in CPU page, and for
COW. They do not support
On 5/23/2022 7:02 AM, Alistair Popple wrote:
Technically I think this patch should be earlier in the series. As I
understand it patch 1 allows DEVICE_COHERENT pages to be inserted in the
page tables and therefore makes it possible for page table walkers to
see non-LRU pages.
Patch will reorde
On 5/20/2022 10:12 AM, Felix Kuehling wrote:
Am 2022-05-20 um 08:45 schrieb philip yang:
On 2022-05-19 19:08, Felix Kuehling wrote:
Am 2022-05-19 um 12:21 schrieb Alex Sierra:
[WHY]
Unified memory with xnack off should be tracked, as userptr mappings
and legacy allocations do. To avoid ov
On 5/11/2022 1:50 PM, Jason Gunthorpe wrote:
On Thu, May 05, 2022 at 04:34:36PM -0500, Alex Sierra wrote:
diff --git a/mm/memory.c b/mm/memory.c
index 76e3af9639d9..892c4cc54dc2 100644
+++ b/mm/memory.c
@@ -621,6 +621,13 @@ struct page *vm_normal_page(struct vm_area_struct *vma,
unsigned lon
On 5/11/2022 9:58 PM, Alistair Popple wrote:
Alex Sierra writes:
[...]
diff --git a/mm/rmap.c b/mm/rmap.c
index fedb82371efe..d57102cd4b43 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -1995,7 +1995,8 @@ void try_to_migrate(struct folio *folio, enum ttu_flags
flags)
@apop...@nvidia.com Could you please check this patch? It's somehow related to
migrate_device_page() for long term device coherent pages.
Regards,
Alex Sierra
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Sierra
> Sent: Thursday, May 5, 2022 4:34 PM
> To: j...@nvidia.com
> Cc:
This v2 patch extends to all GMC versions.
Regards,
Alex
> -Original Message-
> From: Sierra Guiza, Alejandro (Alex)
> Sent: Friday, April 22, 2022 9:25 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Sierra Guiza, Alejandro (Alex)
> Subject: [PATCH v2] drm/amdgpu: repl
On 4/4/2022 12:38 PM, Jason Gunthorpe wrote:
On Fri, Apr 01, 2022 at 04:08:35PM -0400, Felix Kuehling wrote:
In general I find the vm_normal_lru_page vs vm_normal_page
API highly confusing. An explicit check for zone device pages
in the dozen or so spots that care has a much better documenta
Hi Matthew,
I sent this patch by accident. Please ignore it.
Regards,
Alex Sierra
> -Original Message-
> From: Matthew Wilcox
> Sent: Wednesday, March 30, 2022 4:29 PM
> To: Sierra Guiza, Alejandro (Alex)
> Cc: j...@nvidia.com; da...@redhat.com; Kuehling, Felix
> ;
Please ignore this patch.
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Sierra
> Sent: Wednesday, March 30, 2022 4:24 PM
> To: j...@nvidia.com
> Cc: rcampb...@nvidia.com; wi...@infradead.org; da...@redhat.com;
> Kuehling, Felix ; apop...@nvidia.com; amd-
> g...@lists.freedeskto
On 2/11/2022 10:39 AM, David Hildenbrand wrote:
On 11.02.22 17:15, David Hildenbrand wrote:
On 01.02.22 16:48, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a
Christoph,
Thanks a lot for rebase our patches. I just ran our amdgpu hmm-tests
with this series and all passed.
Regards,
Alex Sierra
On 2/10/2022 1:28 AM, Christoph Hellwig wrote:
Hi all,
this series removes the offset by one refcount for ZONE_DEVICE pages
that are freed back to the driver
Hi Alistair,
This is the last patch to be reviewed from this series. It already has
the changes from
your last feedback (V3). Would you mind to take a look?
Thanks a lot for reviewing the rest!
Regards,
Alex Sierra
On 1/28/2022 2:08 PM, Alex Sierra wrote:
Test cases such as migrate_fault and
Andrew,
We're somehow new on this procedure. Are you referring to rebase this
patch series to
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
<5.17-rc1 tag>?
Regards,
Alex Sierra
Alex Deucher,
Just a quick heads up. This patch series contains changes to the amdgpu
driver wh
On 1/20/2022 12:14 AM, Alistair Popple wrote:
On Tuesday, 11 January 2022 9:32:00 AM AEDT Alex Sierra wrote:
Test cases such as migrate_fault and migrate_multiple, were modified to
explicit migrate from device to sys memory without the need of page
faults, when using device coherent type.
Sna
On 12/9/2021 10:29 AM, Felix Kuehling wrote:
Am 2021-12-09 um 5:53 a.m. schrieb Alistair Popple:
On Thursday, 9 December 2021 5:55:26 AM AEDT Sierra Guiza, Alejandro (Alex)
wrote:
On 12/8/2021 11:30 AM, Felix Kuehling wrote:
Am 2021-12-08 um 11:58 a.m. schrieb Felix Kuehling:
Am 2021-12-08
On 12/8/2021 11:30 AM, Felix Kuehling wrote:
Am 2021-12-08 um 11:58 a.m. schrieb Felix Kuehling:
Am 2021-12-08 um 6:31 a.m. schrieb Alistair Popple:
On Tuesday, 7 December 2021 5:52:43 AM AEDT Alex Sierra wrote:
Avoid long term pinning for Coherent device type pages. This could
interfere wit
On 11/2/2021 10:04 AM, philip yang wrote:
On 2021-11-01 10:40 p.m., Alex Sierra wrote:
[Why]:
When we call hmm_range_fault to map memory after a migration, we don't
expect memory to be migrated again as a result of hmm_range_fault. The
driver ensures that all memory is in GPU-accessible loca
On 10/14/2021 3:57 PM, Ralph Campbell wrote:
On 10/14/21 11:01 AM, Jason Gunthorpe wrote:
On Thu, Oct 14, 2021 at 10:35:27AM -0700, Ralph Campbell wrote:
I ran xfstests-dev using the kernel boot option to "fake" a pmem device
when I first posted this patch. The tests ran OK (or at least the
On 9/29/2021 9:15 PM, Felix Kuehling wrote:
On 2021-09-29 7:35 p.m., Mike Lothian wrote:
Hi
This patch is causing a compile failure for me
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.c:1254:25: error:
unused variable 'svms' [-Werror,-Wunused-variable]
struct svm_range_list *svms
On 9/21/2021 12:14 AM, Alistair Popple wrote:
On Tuesday, 21 September 2021 6:05:30 AM AEST Sierra Guiza, Alejandro (Alex)
wrote:
On 9/20/2021 3:53 AM, Alistair Popple wrote:
On Tuesday, 14 September 2021 2:16:01 AM AEST Alex Sierra wrote:
In order to configure device public in test_hmm
On 9/20/2021 3:53 AM, Alistair Popple wrote:
On Tuesday, 14 September 2021 2:16:01 AM AEST Alex Sierra wrote:
In order to configure device public in test_hmm, two module parameters
should be passed, which correspond to the SP start address of each
device (2) spm_addr_dev0 & spm_addr_dev1. If n
On 8/25/2021 2:46 AM, Christoph Hellwig wrote:
On Tue, Aug 24, 2021 at 10:48:17PM -0500, Alex Sierra wrote:
} else {
- if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM))
+ if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM) &&
+
On 8/18/2021 2:28 PM, Ralph Campbell wrote:
On 8/17/21 5:35 PM, Felix Kuehling wrote:
Am 2021-08-17 um 8:01 p.m. schrieb Ralph Campbell:
On 8/12/21 11:31 PM, Alex Sierra wrote:
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that
complicates the
code for put_pag
On 8/15/2021 10:38 AM, Christoph Hellwig wrote:
On Fri, Aug 13, 2021 at 01:31:42AM -0500, Alex Sierra wrote:
migrate.vma = vma;
migrate.start = start;
migrate.end = end;
- migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
migrate.pgmap_owner = SVM_ADEV_PG
On 8/12/2021 1:34 AM, Christoph Hellwig wrote:
Do you have a pointer to a git branch with this series and all dependencies
to ease testing?
Hi Christoph,
Yes, actually tomorrow we're planning to send a new version with
detailed instructions
on how to setup and run each of the tests. This
On 7/22/2021 12:26 PM, Jason Gunthorpe wrote:
On Thu, Jul 22, 2021 at 11:59:17AM -0500, Sierra Guiza, Alejandro (Alex) wrote:
On 7/22/2021 7:23 AM, Jason Gunthorpe wrote:
On Sat, Jul 17, 2021 at 02:21:32PM -0500, Alex Sierra wrote:
In order to configure device generic in test_hmm, two
On 7/17/2021 2:54 PM, Sierra Guiza, Alejandro (Alex) wrote:
On 7/16/2021 5:14 PM, Felix Kuehling wrote:
Am 2021-07-16 um 11:07 a.m. schrieb Theodore Y. Ts'o:
On Wed, Jun 23, 2021 at 05:49:55PM -0400, Felix Kuehling wrote:
I can think of two ways to test the changes for
MEMORY_DEVICE_GE
On 7/22/2021 7:23 AM, Jason Gunthorpe wrote:
On Sat, Jul 17, 2021 at 02:21:32PM -0500, Alex Sierra wrote:
In order to configure device generic in test_hmm, two
module parameters should be passed, which correspon to the
SP start address of each device (2) spm_addr_dev0 &
spm_addr_dev1. If no pa
On 7/16/2021 5:14 PM, Felix Kuehling wrote:
Am 2021-07-16 um 11:07 a.m. schrieb Theodore Y. Ts'o:
On Wed, Jun 23, 2021 at 05:49:55PM -0400, Felix Kuehling wrote:
I can think of two ways to test the changes for MEMORY_DEVICE_GENERIC in
this patch series in a way that is reproducible without spe
On 6/17/2021 6:52 PM, Dave Chinner wrote:
On Thu, Jun 17, 2021 at 10:16:58AM -0500, Alex Sierra wrote:
From: Ralph Campbell
There are several places where ZONE_DEVICE struct pages assume a reference
count == 1 means the page is idle and free. Instead of open coding this,
add a helper functio
On 6/17/2021 10:16 AM, Alex Sierra wrote:
v1:
AMD is building a system architecture for the Frontier supercomputer with a
coherent interconnect between CPUs and GPUs. This hardware architecture allows
the CPUs to coherently access GPU device memory. We have hardware in our labs
and we are worki
2020 5:31 AM
> To: Sierra Guiza, Alejandro (Alex) ; amd-
> g...@lists.freedesktop.org; Koenig, Christian
> Cc: Kuehling, Felix
> Subject: Re: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
>
> Feel free to keep my rb for this, but is 455 days enough in general or s
[AMD Public Use]
I just added support for vega10_ih too.
Regards,
Alex
> -Original Message-
> From: Sierra Guiza, Alejandro (Alex)
> Sent: Tuesday, November 10, 2020 11:55 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Koenig, Christian ; Kuehling, Felix
> ; Sierra Guiz
[AMD Public Use]
Will do Luben. Thanks for the recommendation.
> -Original Message-
> From: Tuikov, Luben
> Sent: Thursday, October 29, 2020 12:15 PM
> To: Sierra Guiza, Alejandro (Alex) ; Koenig, Christian
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/
[AMD Public Use]
Please ignore this patch, it should be in a different branch. As PCIe p2p is
not supported in upstream.
Regards,
Alex Sierra
> -Original Message-
> From: amd-gfx On Behalf Of
> Sierra Guiza, Alejandro (Alex)
> Sent: Wednesday, October 28, 2020 1:09 PM
On 10/28/2020 9:58 AM, Christian König wrote:
Am 28.10.20 um 15:55 schrieb Alex Sierra:
By enabling this parameter, the system will be forced to use pcie
interface only for p2p transactions.
Better name that amdgpu_xgmi with a default value of enabled.
Or maybe add another bit value for amdg
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Sierra
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Wednesday, May 6, 2020 3:12 AM
To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Use GEM obj referenc
[AMD Official Use Only - Internal Distribution Only]
Inline response
-Original Message-
From: Kuehling, Felix
Sent: Friday, March 20, 2020 9:31 AM
To: Sierra Guiza, Alejandro (Alex) ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/amdgpu: add macro to get proper ih ring
[AMD Official Use Only - Internal Distribution Only]
My bad, please ignore this.
I re-sent this in a separate one patch.
Alejandro S
-Original Message-
From: Kuehling, Felix
Sent: Friday, March 20, 2020 9:37 AM
To: Sierra Guiza, Alejandro (Alex) ;
amd-gfx@lists.freedesktop.org
pmf->invalidate_tlbs_size + 8);
I think 12 was too much in the original code. Flush + fence should only be 10
dwords, unless I misses something or counted wrong.
Regards,
Felix
On 2020-01-13 7:48 p.m., Sierra Guiza, Alejandro (Alex) wrote:
> [AMD Official Use Only - Internal Distribution Only]
&
Sent: Monday, January 13, 2020 6:34 PM
To: Sierra Guiza, Alejandro (Alex) ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/7] drm/amdgpu: export function to flush TLB via pasid
Sorry, I already said, Reviewed-by, but realized there was one more problem. If
you haven't submitted yet, pleas
: Friday, January 10, 2020 5:29 AM
To: Sierra Guiza, Alejandro (Alex) ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/8] drm/amdgpu: Avoid reclaim fs while eviction lock
[CAUTION: External Email]
Looks like you send that patch set out twice.
Which one is the most recent one?
Regards
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Koenig, Christian
Sent: Monday, January 6, 2020 10:23 AM
To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org;
Sierra Guiza, Alejandro (Alex)
Subject: Re: [PATCH 2/5] drm/amdgpu: export function to flush
2:52 AM
To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org;
Yang, Philip ; Sierra Guiza, Alejandro (Alex)
Subject: Re: [PATCH 5/5] drm/amdgpu: immedially invalidate PTEs
[CAUTION: External Email]
Hi Felix,
yeah, I've also found a corner case which would raise a warning now.
Need to
Hi Christian,
As you know, we're working on the HMM enablement. Im working on the dGPU page
table entries invalidation on the userptr mapping case. Currently, the MMU
notifiers handle stops all user mode queues, schedule a delayed worker to
re-validate userptr mappings and restart the queues.
Pa
The bitmap in cu_info structure is defined as a 4x4 size array. In
Acturus, this matrix is initialized as a 4x2. Based on the 8 shaders.
In the gpu cache filling initialization, the access to the bitmap matrix
was done as an 8x1 instead of 4x2. Causing an out of bounds memory
access error.
Due to t
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