__kmem_cache_shutdown+0x163/0x2e0
kmem_cache_destroy+0x61/0x170
drm_sched_fence_slab_fini+0x19/0x900
Thus call dma_fence_put properly to avoid the memleak.
v2: call dma_fence_put in amdgpu_gem_va_update_vm
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 9 +++--
1 file changed, 7
__kmem_cache_shutdown+0x163/0x2e0
kmem_cache_destroy+0x61/0x170
drm_sched_fence_slab_fini+0x19/0x900
Thus call dma_fence_put properly to avoid the memleak.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
Add the trap irq processing for page queue of sdma442
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 5e0066cd6c51..14acc3b822ec
Separated xgmi ta is required for specific APU, and driver needs
parse the ta binary properly with aux xgmi ta packed.
v2: make the check function more generic (Lijo)
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 33
This checking is not suitable any more after introducing
psp aux firmware binary.
Signed-off-by: Le Ma
Suggested-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 11 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 --
2 files changed, 13 deletions(-)
diff --git a
parse_sos_bin_descriptor
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 29 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 11 -
2 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b
Query pmfw version to determine if aux sos fw needs to be loaded in psp v13.0.
v2: refine callback to check if aux_fw loading is needed instead of
getting pmfw version barely
v3: return the comparison directly
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu
To adapt to different gc versions in gfx_v9_4_3.c file.
Change-Id: Ib4465aade0dcbbcc43318c6dc865f813c5411097
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
To fix the entity rq NULL issue. This setting has been moved to upper level.
Fixes b70438004a14 ("drm/amdgpu: move buffer funcs setting up a level")
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 20 +---
1 file changed, 1 insertion(+), 19
ng the drm client creation following after drm_dev_register
looks like a more proper flow.
v2: wrap the drm client creation
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 32 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 ++
drivers/gpu/drm/amd/amdgpu/am
ng the drm client creation following after drm_dev_register
looks like a more proper flow.
Change-Id: I0fece177b78345187068f92a823d96b3b7581140
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 ++
drivers/gpu/drm/
This patch is to eliminate interrupt warning below:
"[drm] Fence fallback timer expired on ring sdma0.0".
An early vm pt clearing job is sent to SDMA ahead of interrupt enabled,
introduced by patch below:
- drm/amdkfd: Export DMABufs from KFD using GEM handles
Signed-off
Use debug_mask=0x8 param to help isolating data path issues
on new systems in early phase.
v2: rename the flag for explicitness (lijo)
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++
drivers/gpu/drm/amd/amdgpu
To bring debug options into effect in early initialization phase
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index
se debug_mask=0x8 param to help isolating data path issues
on new systems in early phase.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu/drm/amd/amdgpu
This reverts commit 1797d97a977280ac2cec95b1b59acc5856fea11e.
Will use debug module param instead of independent module param.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
This param can help isolating data path issues on new systems in early phase.
Change-Id: I0a972dd74fe2aad6b56628cea32ad72dcd17e283
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
drivers/gpu/drm/amd/amdgpu
The valid num_mem_partitions is required during ttm pool fini, thus move the
cleanup at the end of the function.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b
The DS clock may exceed the limit as sclk dfll divider is 16 to target freq.
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13
Pass the correct size to smu_v13_0_6_print_clks, otherwise
the same place in buf will be re-written.
Change-Id: Ia0e12430d01146a11490204c1bab4b4f06cd17ea
Signed-off-by: Le Ma
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 24 +--
1 file changed, 12 insertions(+), 12
Replace with set_plpd_mode uniformly for places to use.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 ++--
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 14 --
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 --
drivers/gpu/drm/amd/pm/swsmu
The allow_xgmi_power_down(true/false) will be generally replaced by:
- allow: select_xgmi_plpd_policy(XGMI_PLPD_DEFAULT)
- disallow: select_xgmi_plpd_policy(XGMI_PLPD_DISALLOW)
Signed-off-by: Le Ma
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 21 +
.../drm/amd/pm
: Le Ma
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 43
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 68 +
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 5 ++
3 files changed, 116 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm
Assign DEFAULT mode if it supports plpd, otherwise keeps NONE
v2: reduce ip version checks
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd
Add the interface to change xgmi per-link power down policy.
v2: split from sysfs interface code and miscellaneous updates
v3: check against XGMI_PLPD_DEFAULT/XGMI_PLPD_OPTIMIZED and pass PPSMC param
Signed-off-by: Le Ma
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
Add enum pp_xgmi_plpd_mode to describe PLPD policies.
v2: move the enum from amdgpu_smu.h to kgd_pp_interface.h
Signed-off-by: Le Ma
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 8
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 ++
2 files changed
To add message to select PLPD mode.
Signed-off-by: Le Ma
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu/drm/amd/pm
Several new fields are exposed in gc_info v2_1
Change-Id: Ib320e8ca70de8960634e1a22aaf2611ba7ebbaeb
Signed-off-by: Le Ma
Reviewed-by: Shiwu Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 10 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 ++
drivers/gpu/drm/amd/include
Mall info v2 is introduced in ip discovery
Change-Id: Ia2e49e7679c578065f85059a077fc08c9f84615c
Signed-off-by: Le Ma
Reviewed-by: Shiwu Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +
drivers/gpu/drm/amd/include/discovery.h | 8 +++-
2 files changed, 12 insertions
Handled in earlier phase
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 6be19ffc502b..f413898dda37 100644
--- a/drivers/gpu/drm
Per requested, follow the same sequence as APU to send only
PPSMC_MSG_PrepareForDriverUnload to PMFW during driver unloading.
Change-Id: I2dc8495572b0bce6e21eafb51b215c83d94ac647
Signed-off-by: Le Ma
Reviewed-by: Shiwu Zhang
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/pm/swsmu/smu13
Use fw->size instead of discovery_tmr_size for fallback path.
Change-Id: I61f1ec55314ea5948ed3ef821becfdd63d876272
Signed-off-by: Le Ma
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
From: Le Ma
should count on GC IP base address
Signed-off-by: Le Ma
Signed-off-by: Hawking Zhang
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu
This workaround does not affect other asics because amdgpu only need expose
one gfx sched to user for now.
Change-Id: Ica92b8565a89899aebe0eba7b2b5a25159b411d3
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
baco sequence
Change-Id: I9c08cf90134f940b42e20d2129ff87fba761c532
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 82 +-
2 files changed, 72 insertions(+), 12 deletions(-)
diff --git a/drivers
Switch to baco reset method for ras recovery if baco-supported PMFW ready.
If not, keep the original reset method.
Change-Id: I07c3e6862be03e068745c73db8ea71f428ecba6b
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 18 --
1 file changed, 8 insertions(+), 10
Move the print out of uvd instance loop in amdgpu_uvd_suspend
v2: drop unnecessary brackets
v3: grab ras_intr state once for multiple times use
Change-Id: Ifad997debd84763e1b55d668e144b729598f115e
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 11 +++
1 file changed
Move the print out of uvd instance loop in amdgpu_uvd_suspend
v2: drop unnecessary brackets
Change-Id: Ifad997debd84763e1b55d668e144b729598f115e
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a
This athub fatal error can be recovered by baco without system-level reboot,
so add a mode to use baco for the recovery. Not affect the default psp reset
situations for now.
Change-Id: Ib17f2a39254ff6b0473a785752adfdfea79d0e0d
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-supported smu firmware
The case that PSP reset and baco reset coexist within an XGMI hive is not in
the consideration.
Change-Id: I9c08cf90134f940b42e20d2129ff87fba761c532
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 78
Change it to external interface.
Change-Id: I2ab61f149c84a05a6f883a4c7415ea8012ec03a6
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 +++
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd
Otherwise next err_event_athub error cannot call gpu reset. And following
resume sequence will not be affected by this flag.
v2: create function to clear amdgpu_ras_in_intr for modularity of ras driver
Change-Id: I5cd293f30f23876bf2a1860681bcb50f47713ecd
Signed-off-by: Le Ma
---
drivers/gpu
This operation is needed when baco entry/exit for ras recovery
Change-Id: I535c7231693f3138a8e3d5acd55672e2ac68232f
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Le Ma
v2: add notification when ras controller interrupt generates
Change-Id: Ic03e42e9d1c4dab1fa7f4817c191a16e485b48a9
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
Move the print out of uvd instance loop in amdgpu_uvd_suspend
Change-Id: Ifad997debd84763e1b55d668e144b729598f115e
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b
Avoid to change default reset behavior for production card by checking
amdgpu_ras_enable equal to 2. And only new enough smu ucode can support
baco for xgmi/ras case.
Change-Id: I07c3e6862be03e068745c73db8ea71f428ecba6b
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1
To fix issue that ras controller interrupt cannot be triggered anymore after
one time nbif uncorrectable error. And error count is stored in nbif ras object
for query.
Change-Id: Iba482c169fdff3e9c390072c0289a622a522133c
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10
Set mmSQ_CONFIG.DISABLE_SMEM_SOFT_CLAUSE as W/R.
Change-Id: I6225909fd62702427fbb807e0c6ba6bafcfa41d5
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
Fix compilation error.
Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index fce206f
From: Le Ma
Change-Id: Ia8a61a4b3bd529f0f691e43e69b299d7d151c0c2
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index
The err_event_athub error will mess up the buffer and cause UVD resume hang.
Change-Id: If17a2161fb9b1b52eac08de00d2e935191bdbf99
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
PSP lost connection when err_event_athub occurs. These cleanup work can be
skipped in BACO reset.
Change-Id: If54a3735edd6ccbb58d40a5f8833392981f8ce37
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 7
Otherwise next err_event_athub error cannot call gpu reset.
Change-Id: I5cd293f30f23876bf2a1860681bcb50f47713ecd
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu
Workaround to make RAS recovery work in BACO reset.
Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 8
drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
3
1 indicates RAS recovery flag in SMU FW.
Change-Id: Icb8c14586fca1b8ae443bbde764570a9e41850fa
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.
Change-Id: I2a82c128fa5e9731b886dd61f1273dc48ea1923c
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/powerplay/hwmgr
BACO reset is needed for RAS recovery.
Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
b/drivers/gpu/drm
Change-Id: Ia91d0fb7179f6944214e892f370d7ef3d6b7d30e
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d359f1d..2aa1ae6
From: Hawking Zhang
Change-Id: I88649fc5dbc7376f3c90ec2114236294ca9189de
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu
Change-Id: I6b69bfba66aa12d5486527e29a7c322336c95dd5
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 5bec851..dbd790e 100644
--- a/drivers/gpu/drm/amd
Change-Id: Ibf137cd57659e70516bcbbe456a00ad77e60647c
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7c7e9f5..5bec851 100644
--- a
Change-Id: I13a5f590d5a49655965a13eb7ce773d1efffcbd0
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 82f6b41
Follow the hw spec, and no need to consider gfxoff on Arcturus
Change-Id: Ib9cad79b1b9c096014447fc0a7d29cdb594e15e3
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b
Follow patch below:
drm/amd/powerplay: re-define smu interface version for smu v11
Change-Id: Id78651209adc7a094f4c19ba965dcded37dd3ba7
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 -
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
Init MC_MGCG/LS flag. Also apply to athub CG.
Change-Id: Ic00cb8e6d69eb75dd32f34f778352cee93063ee0
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 1 -
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
drm/amdgpu: enable gfx clock gating for Arcturus
Change-Id: I9d70319dd07f7d642416cb260f9f5b3342b6f3f2
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
Add 2 mmhub instances CG
Change-Id: I76ab7a50cd9a40de3022f733787b42e4e5c4dbf5
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +--
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 126
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h | 3 +
3 files
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic
not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info.
Change-Id: I4ba970cae558ad5163e93fa9bc77f589196a22b1
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers
Init hdp MGCG/LS flag as Vega20
Change-Id: Ia33ca064f79ac409c53d3beb6f01b6e814a92041
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
Add hdp CGLS for Arcturus in set common clockgating function
Change-Id: I44e392fa5f7653908b36b0902e721d56eed3eb92
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers
Init gfx MGCG/LS, CGCG/LS, CP_LS flag.
Change-Id: I88db76d1b8f2b2cecce10846a4d22eec638eea8a
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15
Add ARCTURUS case in sdma set clockgating function
Change-Id: I65a3d99a140a8a76949b4d03c20bc6e0195c9854
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu
Init sdma MGCG/LS flag
Change-Id: I600b8c67b1dfa74240269f2f028960b2c93a0ec2
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6038dce
Add ARCTURUS case in gfx set clockgating function. No 3d clock on Arcturus.
Change-Id: I9893a2afea7f0b5d433baa14f48ae55a36516fac
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b
Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.
Change-Id: Icbf94169bb703877b105a307f14c708609faaae4
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 105 +++--
1 file changed, 34 insertions(+), 71 deletions(-)
diff --git a/drivers
Change-Id: I502cc5fde7f00e41d496bfba0963d4db20459e00
Signed-off-by: Le Ma
---
tests/amdgpu/amdgpu_test.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index a4ce8ce..dc54155 100644
--- a/tests/amdgpu
for better clarification
v2: accordingly change dispatch_test caller in gpu_reset test
Change-Id: I245d760d5f9d64eb10b137d5ce375ef52a4d873a
Signed-off-by: Le Ma
Reviewed-by: Flora Cui
---
tests/amdgpu/basic_tests.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions
for better clarification
Change-Id: I245d760d5f9d64eb10b137d5ce375ef52a4d873a
Signed-off-by: Le Ma
---
tests/amdgpu/basic_tests.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 938106e..fa0f568
From: Le Ma
The rlc reset function is not necessary during gfx9 initialization/resume phase.
And this function would even cause rlc fw loading failed on some gfx9 ASIC.
Remove this function safely with verification well on Vega/Raven platform.
Change-Id
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