On 10/01/2025 19:37, Jay Cornwall wrote:
On 1/10/2025 12:14, Six, Lancelot wrote:
If user shader issues S_SETVSKIP then this state will persist when
executing the trap handler, causing vector instructions to be
skipped.
Restore VSKIP state before resuming the user shader.
Hi,
I agree wit
On 09/01/2025 17:56, Jay Cornwall wrote:
Source and binary have become mismatched during branch activity.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Thanks for doing that. That new binary match what I obtain by
re-assembling the sources.
Reviewed-by: Lancelot Six
Best,
Lancelot
fixes
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Cc: Jonathan Kim
Hi,
I scanned through the patch, it seems reasonable to me, and comments
from V1 seem addressed. When assembled, I obtain the same binary for
the trap handler, so no functional changes. Thanks for doing that.
Reviewed-By
implementations from gfx10/gfx11. Add a separate source file for
gfx12+ and remove unneeded conditional code.
No functional change.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Cc: Jonathan Kim
---
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 202 +--
.../amd/amdkfd/cwsr_trap_handler_gfx12.asm
te TRAPSTS.{SAVECTX,HOST_TRAP} when restoring this
register. Both of these fields can assert while the wavefront is
running the trap handler.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Hi Jay,
Thanks, that looks good to me (tested on gfx10.3, 11 and 12). For
gfx11+ there might be a risk of
-next, but I guess we just have a
different bases.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 695 +-
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 17 +
2 files changed, 366 insertions(+), 346 deletions(-)
diff --git
On 23/05/2024 20:31, Jay Cornwall wrote:
On 5/23/2024 13:37, Lancelot SIX wrote:
@@ -622,8 +638,15 @@ L_SAVE_HWREG:
#if ASIC_FAMILY >= CHIP_GFX12
// Ensure no further changes to barrier or LDS state.
+ // STATE_PRIV.BARRIER_COMPLETE may change up to this po
On 23/05/2024 15:08, Jay Cornwall wrote:
Newer assemblers reject S_WAITCNT. All instances of S_WAITCNT can be
replaced by S_WAITCNT 0 (< gfx12) or S_WAIT_IDLE (>= gfx12) since
there is no concurrency of different memory instruction classes.
Signed-off-by: Jay Cornwall
Cc: Lancel
On 23/05/2024 15:08, Jay Cornwall wrote:
Source and binary have become mismatched during branch activity.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Thanks for doing this.
This matches what I have when rebuilding the trap handlers.
Reviewed-by: Lancelot Six
---
.../gpu/drm/amd
e this field
to assert if they complete the barrier.
Do not overwrite EXCP_FLAG_PRIV.{SAVE_CONTEXT,HOST_TRAP} when
restoring this register. Both of these fields can assert while the
wavefront is running the trap handler.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/
gfx940 assembler.
This patch updates the cwsr_trap_handler_gfx9.s source file to be
compatible with all gfx9 variants of the ISA. The binary assembled code
is unchanged (so the behaviour is unchanged as well), only the source
representation is updated.
Signed-off-by: Lancelot SIX
---
.../drm
et by kfd_process_wq_release.
This patch proposes to avoid this race by making sure to drain
kfd_process_wq before creating a new kfd_process object. This way, we
know that any cleanup task is done executing when we reach
kobject_init_and_add.
Signed-off-by: Lancelot SIX
---
drivers/gpu/drm/amd/a
*_BIT_GFX10) as this reflects what both TCP and
SQ watchpoints can do and both watchpoints are configured together.
Signed-off-by: Lancelot SIX
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 71 +++
1 file changed, 58 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd
The trap handler could be entered with pending VALU exceptions, so
clear the exception state before issuing vector instructions.
Signed-off-by: Laurent Morichetti
Reviewed-by: Jay Cornwall
Hi,
FYI, I tested this and it fixes the issue.
Best,
Lancelot.
Tested-by: Lancelot Six
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