[Public]
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
From: Mahfooz, Hamza
Sent: Friday, March 22, 2024 2:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kazlauskas, Nicholas ; Li, Roman
; Li, Sun peng (Leo) ; Wentland, Harry
; Deucher
[Public]
This bug previously existed, and we have a solution in place for it.
The solution we picked was to force a stall through reading back the memory.
You'll see this implemented in dmub_srv.c and the dmub_cmd.h header - through
use of a volatile read over the region written. We do this for
[AMD Official Use Only]
> -Original Message-
> From: Melissa Wen
> Sent: Friday, March 25, 2022 4:45 PM
> To: amd-gfx@lists.freedesktop.org; Wentland, Harry
> ; Deucher, Alexander
> ; Siqueira, Rodrigo
> ; Kazlauskas, Nicholas
> ; Gutierrez, Agustin
>
On 2/3/2022 5:14 PM, roman...@amd.com wrote:
From: Roman Li
[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...
Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg i
On 1/18/2022 11:40 AM, Rodrigo Siqueira wrote:
From: Leo Li
[Why]
crc_skip_count is used to track how many frames to skip to allow the OTG
CRC engine to "warm up" before it outputs correct CRC values.
Experimentally, this seems to be 2 frames.
When duplicating CRTC states, this value was not c
[Public]
> -Original Message-
> From: Limonciello, Mario
> Sent: January 14, 2022 10:38 AM
> To: Chris Hixon ; Kazlauskas, Nicholas
> ; amd-gfx@lists.freedesktop.org
> Cc: Zhuo, Qingqing (Lillian) ; Scott Bruce
> ; spassw...@web.de
> Subject: RE: [PATCH v5] drm
On 2022-01-07 4:40 p.m., Mario Limonciello wrote:
Otherwise future commands may fail as well leading to downstream
problems that look like they stemmed from a timeout the first time
but really didn't.
Signed-off-by: Mario Limonciello
I guess we used to do this but after we started adding the
[AMD Official Use Only]
> -Original Message-
> From: Limonciello, Mario
> Sent: January 7, 2022 11:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario ; Kazlauskas, Nicholas
> ; Zhuo, Qingqing (Lillian)
> ; Scott Bruce ; Chris
> Hixon ; spassw...@
On 2021-12-07 1:55 p.m., Fangzhi Zuo wrote:
It is w/a to check DP2 SST behavior on M42d box.
Isn't this useful beyond just the m42d/dp2?
This should affect regular DP MST support I think. Adding this debug
flag is okay I think, but I think the names should be updated (inline).
Signed-off-
On 2021-12-02 7:52 a.m., Vlad Zahorodnii wrote:
dm_check_crtc_cursor() doesn't take into account plane transforms when
calculating plane scaling, this can result in false positives.
For example, if there's an output with resolution 3840x2160 and the
output is rotated 90 degrees, CRTC_W and CRTC_
On 2021-11-26 9:32 a.m., Fangzhi Zuo wrote:
Change since v1: add brief description
1. Add hdmi frl pcon support to existing asic family.
2. Determine pcon frl capability based on pcon dpcd.
3. pcon frl is taken into consideration into mode validation.
Signed-off-by: Fangzhi Zuo
Reviewed-by: N
On 2021-11-24 12:28 p.m., Fangzhi Zuo wrote:
1. Parse DSC caps from PCON DPCD
2. Determine policy if decoding DSC at PCON
3. Enable/disable DSC at PCON
Signed-off-by: Fangzhi Zuo
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_d
On 2021-11-12 10:56 a.m., Leo (Hanghong) Ma wrote:
[Why & How]
Dmesg errors are found on dcn3.1 during reset test, but it's not
a really failure. So reduce it to a debug print.
Signed-off-by: Leo (Hanghong) Ma
This is expected to occur on displays that aren't connected/don't
support LTTPR so
On 2021-10-28 10:46 a.m., Alex Deucher wrote:
Ping
On Wed, Oct 27, 2021 at 6:40 PM Alex Deucher wrote:
Need to guard some things with CONFIG_DRM_AMD_DC_DCN.
Fixes: 0c865d1d817b77 ("drm/amd/display: fix link training regression for 1 or 2
lane")
Signed-off-by: Alex Deucher
Reviewed-by: Ni
On 2021-10-28 10:46 a.m., Alex Deucher wrote:
ping
On Wed, Oct 27, 2021 at 6:40 PM Alex Deucher wrote:
Need to guard some things with CONFIG_DRM_AMD_DC_DCN.
Fixes: 707021dc0e16f6 ("drm/amd/display: Enable dpia in dmub only for DCN31 B0")
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas K
On 2021-10-26 11:51 a.m., Michel Dänzer wrote:
On 2021-10-26 13:07, Stylon Wang wrote:
[Why]
In GNOME Settings->Display the switching from mirror mode to single display
occasionally causes wait_for_completion_interruptible_timeout() to return
-ERESTARTSYS and fails atomic check.
[How]
Replace t
On 2021-10-26 7:07 a.m., Stylon Wang wrote:
[Why]
In GNOME Settings->Display the switching from mirror mode to single display
occasionally causes wait_for_completion_interruptible_timeout() to return
-ERESTARTSYS and fails atomic check.
[How]
Replace the call with wait_for_completion_timeout() s
On 2021-10-25 9:58 a.m., Harry Wentland wrote:
On 2021-10-25 07:25, Paul Menzel wrote:
Dear Wenjing, dear Rodrigo,
On 24.10.21 15:31, Rodrigo Siqueira wrote:
From: Wenjing Liu
[why]
We have a regression that cause maximize lane settings to use
uninitialized data from unused lanes.
Which
On 2021-10-20 9:53 a.m., Alex Deucher wrote:
Fix revision id.
Fixes: 626cbb641f1052 ("drm/amdgpu: support B0&B1 external revision id for yellow
carp")
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/include/dal_a
On 2021-10-15 7:53 p.m., Mike Lothian wrote:
This patch seems to change z8 - not that I know what z8 or z9 are
It's a little misleading but the patch and terminology is correct.
Z9 is the usecase for these watermarks even if the calculation is shared
with Z8/Z9.
Regards,
Nicholas Kazlauskas
On 2021-10-11 1:04 a.m., Vishwakarma, Pratik wrote:
On 10/8/2021 9:44 PM, Nicholas Kazlauskas wrote:
[Why]
New idle optimizations for DCN3.1 require PSR for optimal power savings
on panels that support it.
This was previously left disabled by default because of issues with
compositors that do
On 2021-09-13 3:13 p.m., Alex Deucher wrote:
Acked-by: Alex Deucher
Can you add a fixes: tag?
Alex
Sure, I think the relevant patch is:
Fixes: 64b1d0e8d50 ("drm/amd/display: Add DCN3.1 HWSEQ")
Regards,
Nicholas Kazlauskas
On Mon, Sep 13, 2021 at 3:11 PM Nicholas Kazlauskas
wrote:
[Wh
On 2021-09-07 10:19 a.m., Simon Ser wrote:
In amdgpu_dm_atomic_check, dc_validate_global_state is called. On
failure this logs a warning to the kernel journal. However warnings
shouldn't be used for atomic test-only commit failures: user-space
might be perfoming a lot of atomic test-only commits
On 2021-09-04 10:36 a.m., Mike Lothian wrote:
Hi
This patch is causing issues on my PRIME system
I've opened
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1700&data=04%7C01%7Cnicholas.kazlauskas%40amd.com%7Cd230db90a08d4b530
On 2021-08-24 9:59 a.m., Simon Ser wrote:
Hi Rodrigo!
Thanks a lot for your reply! Comments below, please bear with me: I'm
a bit familiar with the cursor issues, but my knowledge of AMD hw is
still severely lacking.
On Wednesday, August 18th, 2021 at 15:18, Rodrigo Siqueira
wrote:
On 08/18
On 2021-08-19 2:58 p.m., Fangzhi Zuo wrote:
Parse DP2 encoder caps and hpo instance from bios
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 10 ++
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 10 ++
.../drm/amd/display/dc
On 2021-08-16 4:59 p.m., Fangzhi Zuo wrote:
HW Blocks:
++ +-+ +--+
| OPTC | | HDA | | HUBP |
++ +-+ +--+
| ||
| ||
HPO |==||
| |
On 2021-06-21 4:58 p.m., Alex Deucher wrote:
No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/Kconfig
On 2021-06-04 2:16 p.m., Alex Deucher wrote:
Missing proper DC_FP_START/DC_FP_END.
Signed-off-by: Alex Deucher
Thanks for catching these.
Series is Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 18 +-
On 2021-05-21 12:08 a.m., Alex Deucher wrote:
Avoid spamming the log. The backlight controller on DCN chips
gets powered down when the display is off, so if you attempt to
set the backlight level when the display is off, you'll get this
message. This isn't a problem as we cache the requested ba
On 2021-05-19 4:55 p.m., Aurabindo Pillai wrote:
[Why]
Conditions that end up modifying the global dc state must be locked.
However, during mst allocate payload sequence, lock is already taken.
With StarTech 1.2 DP hub, we get an HPD RX interrupt for a reason other
than to indicate down reply ava
On 2021-05-07 10:39 a.m., Rodrigo Siqueira wrote:
The amdgpu_dm file contains most of the code that works as an interface
between DRM API and Display Core. We maintain all the plane operations
inside amdgpu_dm; this commit extracts the plane code to its specific
file named amdgpu_dm_plane. This c
On 2021-05-07 10:37 a.m., Rodrigo Siqueira wrote:
Currently, we reject all conditions where the underlay plane goes
outside the overlay plane limits, which is not entirely correct since we
reject some valid cases like the ones illustrated below:
++ ++
On 2021-04-22 7:20 p.m., Harry Wentland wrote:
[Why]
This hasn't been well tested and leads to complete system hangs on DCN1
based systems, possibly others.
The system hang can be reproduced by gesturing the video on the YouTube
Android app on ChromeOS into full screen.
[How]
Reject atomic comm
eloper testing we can hardcode the flag = true, I think the DC
debug flags here in AMDGPU base driver only have value if we want
general end user or validation to use this to debug potential issues.
Regards,
Nicholas Kazlauskas
Thanks,
Best Regards,
Jude
-Original Message-
From:
On 2021-04-06 9:40 a.m., Jude Shih wrote:
[Why & How]
We use outbox interrupt that allows us to do the AUX via DMUB
Therefore, we need to add some irq source related definition
in the header files;
Also, I added debug flag that allows us to turn it on/off
for testing purpose.
Signed-off-by: Jude
On 2021-03-31 11:21 p.m., Jude Shih wrote:
[Why & How]
We use outbox interrupt that allows us to do the AUX via DMUB
Therefore, we need to add some irq source related definition
in the header files;
Also, I added debug flag that allows us to turn it on/off
for testing purpose.
Missing your sign
On 2021-03-08 3:18 p.m., Daniel Vetter wrote:
On Fri, Mar 5, 2021 at 10:24 AM Michel Dänzer wrote:
On 2021-03-04 7:26 p.m., Kazlauskas, Nicholas wrote:
On 2021-03-04 10:35 a.m., Michel Dänzer wrote:
On 2021-03-04 4:09 p.m., Kazlauskas, Nicholas wrote:
On 2021-03-04 4:05 a.m., Michel Dänzer
On 2021-03-04 1:41 p.m., Alex Deucher wrote:
On Thu, Mar 4, 2021 at 1:33 PM Kazlauskas, Nicholas
wrote:
On 2021-03-04 12:41 p.m., Alex Deucher wrote:
It just spams the logs.
Signed-off-by: Alex Deucher
This series in general looks reasonable to me:
Reviewed-by: Nicholas Kazlauskas
On 2021-03-04 12:41 p.m., Alex Deucher wrote:
It just spams the logs.
Signed-off-by: Alex Deucher
This series in general looks reasonable to me:
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/
On 2021-03-04 10:35 a.m., Michel Dänzer wrote:
On 2021-03-04 4:09 p.m., Kazlauskas, Nicholas wrote:
On 2021-03-04 4:05 a.m., Michel Dänzer wrote:
On 2021-03-03 8:17 p.m., Daniel Vetter wrote:
On Wed, Mar 3, 2021 at 5:53 PM Michel Dänzer wrote:
Moreover, in the same scenario plus an overlay
On 2021-03-04 4:05 a.m., Michel Dänzer wrote:
On 2021-03-03 8:17 p.m., Daniel Vetter wrote:
On Wed, Mar 3, 2021 at 5:53 PM Michel Dänzer wrote:
On 2021-02-19 7:58 p.m., Simon Ser wrote:
Make sure there's an underlying pipe that can be used for the
cursor.
Signed-off-by: Simon Ser
Cc: Alex
On 2021-02-12 8:08 p.m., Aurabindo Pillai wrote:
[Why]
A seamless transition between modes can be performed if the new incoming
mode has the same timing parameters as the optimized mode on a display with a
variable vtotal min/max.
Smooth video playback usecases can be enabled with this seamless
On 2021-02-23 10:22 a.m., Alex Deucher wrote:
Missing some CONFIG_DRM_AMD_DC_DCN ifdefs.
Fixes: 9d99a805a9a0 ("drm/amd/display: Fix system hang after multiple hotplugs")
Signed-off-by: Alex Deucher
Cc: Stephen Rothwell
Cc: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas K
On 2021-02-20 1:30 a.m., ZhiJie.Zhang wrote:
Signed-off-by: ZhiJie.Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index c103f8583
On 2021-02-19 12:29 p.m., Simon Ser wrote:
On Friday, February 19th, 2021 at 6:22 PM, Kazlauskas, Nicholas
wrote:
We can support cursor plane, but only if we have an overlay plane
enabled that's using XRGB/ARGB.
This is what we do on Chrome OS for video playback:
Cursor Plane - ARG
On 2021-02-19 11:19 a.m., Simon Ser wrote:
The cursor plane can't be displayed if the primary plane isn't
using an RGB format. Reject such atomic commits so that user-space
can have a fallback instead of an invisible cursor.
In theory we could support YUV if the cursor is also YUV, but at the
mo
On 2021-02-10 9:25 a.m., Alex Deucher wrote:
This reverts commit 8866a67ab86cc0812e65c04f1ef02bcc41e24d68.
This breaks hotplug of HDMI on some systems, resulting in
a blank screen.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211649>> Signed-off-by: Alex Deucher
---
Hotplug is still wor
On 2021-02-08 2:25 p.m., Anson Jacob wrote:
This reverts commit de6571ecbb88643fa4bb4172e65c12795a2f3124.
Patch causes regression in resume time.
Shouldn't affect any system that has an eDP connector on the board since
it's expected to be present in end user configuration.
If we want to rep
On 2021-01-24 11:00 p.m., Aurabindo Pillai wrote:
On 2021-01-21 2:05 p.m., Kazlauskas, Nicholas wrote:
On 2021-01-19 10:50 a.m., Aurabindo Pillai wrote:
[Why]
A seamless transition between modes can be performed if the new incoming
mode has the same timing parameters as the optimized mode on
On 2021-01-25 12:57 p.m., Alex Deucher wrote:
On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner
wrote:
This fixes corrupted display output in HDMI deep color
10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.
It will hopefully also provide fixes for other DCE's up to
DCE-11, assuming th
On 2021-01-19 10:50 a.m., Aurabindo Pillai wrote:
[Why]
A seamless transition between modes can be performed if the new incoming
mode has the same timing parameters as the optimized mode on a display with a
variable vtotal min/max.
Smooth video playback usecases can be enabled with this seamless
On 2021-01-20 5:26 a.m., Christian König wrote:
Am 19.01.21 um 21:40 schrieb Bhawanpreet Lakha:
From: Harry Wentland
[Why]
DC needs to communicate with PM FW through GPU memory. In order
to do so we need to be able to allocate memory from within DC.
[How]
Call amdgpu_bo_create_kernel to alloc
On 2021-01-19 3:40 p.m., Bhawanpreet Lakha wrote:
From: Harry Wentland
[Why]
DC needs to communicate with PM FW through GPU memory. In order
to do so we need to be able to allocate memory from within DC.
[How]
Call amdgpu_bo_create_kernel to allocate GPU memory and use a
list in amdgpu_display
On 2021-01-19 3:38 p.m., Bhawanpreet Lakha wrote:
Update the function for idle optimizations
-remove hardcoded size
-enable no memory-request case
-add cursor copy
-update mall eligibility check case
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Joshua Aberback
Series is:
Reviewed-by: Nic
On 2021-01-12 11:13 a.m., Bhawanpreet Lakha wrote:
[Why]
during idle optimizations we acquire the dc_lock, this lock is also
acquired during gpu_reset so we end up hanging the system due to a
deadlock
[How]
If we are in gpu reset:
- disable idle optimizations and skip calls to the dc function
On 2021-01-11 2:55 p.m., Bhawanpreet Lakha wrote:
[Why]
during idle optimizations we acquire the dc_lock, this lock is also
acquired during gpu_reset so we end up hanging the system due to a
deadlock
[How]
If we are in gpu reset dont acquire the dc lock, as we already have it
Are we sure this
On 2021-01-08 11:33 a.m., Alex Deucher wrote:
dc_allow_idle_optimizations() needs to be protected by
CONFIG_DRM_AMD_DC_DCN.
Reported-by: Stephen Rothwell
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/
On 2021-01-04 4:08 p.m., Aurabindo Pillai wrote:
[Why&How]
Inorder to enable freesync video mode, driver adds extra
modes based on preferred modes for common freesync frame rates.
When commiting these mode changes, a full modeset is not needed.
If the change in only in the front porch timing valu
*From:* amd-gfx on behalf of
Sasha Levin
*Sent:* Tuesday, December 22, 2020 9:16 PM
*To:* linux-ker...@vger.kernel.org ;
sta...@vger.kernel.org
*Cc:* Sasha Levin ; dri-de...@lists.freedesktop.org
; amd-gfx@lists.freedesktop.org
; Bas Nieuwenhuizen
; Deucher, Alexander
; Kazla
On 2020-12-28 1:50 p.m., Mario Kleiner wrote:
The hw supports fp16, this is not only useful for HDR,
but also for standard dynamic range displays, because
it allows to get more precise color reproduction with
about 11 - 12 bpc linear precision in the unorm range
0.0 - 1.0.
Working fp16 scanout+d
On 2020-12-28 1:50 p.m., Mario Kleiner wrote:
This takes hw constraints specific to pixel formats into account,
e.g., the inability of older hw to scale fp16 format framebuffers.
It should now allow safely to enable fp16 formats also on DCE-8,
DCE-10, DCE-11.0
Signed-off-by: Mario Kleiner
Re
On 2020-12-09 9:45 p.m., Aurabindo Pillai wrote:
[Why&How]
Inorder to enable freesync video mode, driver adds extra
modes based on preferred modes for common freesync frame rates.
When commiting these mode changes, a full modeset is not needed.
If the change in only in the front porch timing valu
On 2020-12-11 12:54 a.m., Shashank Sharma wrote:
On 11/12/20 12:18 am, Aurabindo Pillai wrote:
[Why&How]
If experimental freesync video mode module parameter is enabled, add
few extra display modes into the driver's mode list corresponding to common
video frame rates. When userspace sets these
On 2020-12-09 9:45 p.m., Aurabindo Pillai wrote:
[Why&How]
Adds a module parameter to enable experimental freesync video mode modeset
optimization. Enabling this mode allows the driver to skip a full modeset when
freesync compatible modes are requested by the userspace. This paramters also
adds s
On 2020-12-21 10:18 p.m., Zhan Liu wrote:
[Why]
Driver cannot change amdgpu framebuffer (afb) format while doing
page flip. Force system doing so will cause ioctl error, and result in
breaking several functionalities including FreeSync.
If afb format is forced to change during page flip, followi
*From:* Wang, Chao-kai (Stylon)
*Sent:* Tuesday, November 10, 2020 2:49 AM
*To:* amd-gfx@lists.freedesktop.org
*Cc:* Wang, Chao-kai (Stylon) ; Kazlauskas,
Nicholas ; Deucher, Alexander
; Wentland, Harry
*Subject:* [PATCH] drm/amd/display: Fix
On 2020-12-11 10:35 a.m., Shashank Sharma wrote:
On 11/12/20 8:19 pm, Kazlauskas, Nicholas wrote:
On 2020-12-11 12:08 a.m., Shashank Sharma wrote:
On 10/12/20 11:20 pm, Aurabindo Pillai wrote:
On Thu, 2020-12-10 at 18:29 +0530, Shashank Sharma wrote:
On 10/12/20 8:15 am, Aurabindo Pillai
On 2020-12-11 12:08 a.m., Shashank Sharma wrote:
On 10/12/20 11:20 pm, Aurabindo Pillai wrote:
On Thu, 2020-12-10 at 18:29 +0530, Shashank Sharma wrote:
On 10/12/20 8:15 am, Aurabindo Pillai wrote:
[Why&How]
Inorder to enable freesync video mode, driver adds extra
modes based on preferred mod
On 2020-12-07 3:03 p.m., roman...@amd.com wrote:
From: Roman Li
[Why]
Scatter/gather feature is supported on Vangogh.
[How]
Add GTT domain support for Vangogh to enable
display buffers in system memory.
Signed-off-by: Roman Li
Series is:
Reviewed-by: Nicholas Kazlauskas
Regards,
Nichola
On 2020-12-04 9:30 a.m., Alex Deucher wrote:
To avoid a recently added warning:
Bogus possible_crtcs: [ENCODER:65:TMDS-65] possible_crtcs=0xf (full crtc
mask=0x7)
WARNING: CPU: 3 PID: 439 at drivers/gpu/drm/drm_mode_config.c:617
drm_mode_config_validate+0x178/0x200 [drm]
In this case the wa
On 2020-12-03 3:19 p.m., Simon Ser wrote:
Previously we accepted non-linear buffers for the cursor plane. This
results in bad output, DC validation failures and oops.
Make sure the FB uses a linear layout in the atomic check function.
The GFX8- check is inspired from ac_surface_set_bo_metadata
On 2020-12-02 4:09 p.m., Simon Ser wrote:
Replace the width check with a pitch check, which matches DM internals.
Add a new check to make sure the pitch (in pixels) matches the width.
Signed-off-by: Simon Ser
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Nicholas Kazlauskas
Series is:
Reviewed-
On 2020-11-26 7:18 p.m., Aurabindo Pillai wrote:
[Why&How]
Set dpms off on the MST connector that was unplugged, for the side effect of
releasing some references held through deallocation of mst payload.
Applies to non-MST now too, so the description and title should be updated.
Signed-off-
On 2020-11-26 4:45 p.m., Aurabindo Pillai wrote:
[Why&How]
Set dpms off on the MST connector that was unplugged, for the side effect of
releasing some references held through deallocation of mst payload.
Signed-off-by: Aurabindo Pillai
Signed-off-by: Eryk Brol
---
.../gpu/drm/amd/display/am
On 2020-11-26 2:50 p.m., Aurabindo Pillai wrote:
[Why&How]
Set dpms off on the MST connector that was unplugged, for the side effect of
releasing some references held through deallocation of mst payload.
Signed-off-by: Aurabindo Pillai
Signed-off-by: Eryk Brol
---
.../gpu/drm/amd/display/am
On 2020-11-26 9:31 a.m., Aurabindo Pillai wrote:
[Why&How]
Recent changes to upstream mst code remove the callback which
cleared the internal state for mst. Move the missing functionality
that was previously called through the destroy call back for mst connector
destroy
Signed-off-by: Aurabindo
On 2020-11-13 3:27 p.m., Bhawanpreet Lakha wrote:
There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/
On 2020-11-12 5:06 p.m., Bhawanpreet Lakha wrote:
From: Alex Deucher
Adjust the FP handling to avoid nested calls.
The nested calls cause the warning below
WARNING: CPU: 3 PID: 384 at arch/x86/kernel/fpu/core.c:129 kernel_fpu_begin
Fixes: 26803606c5d6 ("drm/amdgpu/display: FP fixes for DCN3.x
On 2020-11-13 2:23 a.m., Alex Deucher wrote:
If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
On 2020-11-12 3:56 p.m., Alex Deucher wrote:
On Thu, Nov 12, 2020 at 3:07 PM Simon Ser wrote:
CC Daniel Vetter and Bas, see below…
On Thursday, November 12, 2020 8:56 PM, Kazlauskas, Nicholas
wrote:
Reviewed-by: Nicholas kazlauskasnicholas.kazlaus...@amd.com
Thanks for the review
On 2020-11-12 12:37 p.m., Simon Ser wrote:
This patch expands the cursor checks added in "drm/amd/display: add basic
atomic check for cursor plane" to also include a pitch check. Without
this patch, setting a FB smaller than max_cursor_size with an invalid
pitch would result in amdgpu error messa
On 2020-11-02 5:28 p.m., Alex Deucher wrote:
Add proper FP_START/END handling and adjust Makefiles per
previous asics.
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 13
.../drm/amd/disp
On 2020-11-02 1:49 p.m., Alex Deucher wrote:
Ping?
Alex
On Tue, Oct 27, 2020 at 11:04 AM Alex Deucher wrote:
Properly protect the relevant code with CONFIG_DRM_AMD_DC_DCN.
Fixes: 0b08c54bb7a3 ("drm/amd/display: Fix the display corruption issue on
Navi10")
Signed-off-by: Alex Deucher
Rev
On 2020-10-30 2:55 a.m., Pratik Vishwakarma wrote:
[Why]
Incorrect values were resulting in flash lines
when MPO was enabled and system was left idle.
[How]
Increase min clk values only when MPO is enabled
and display is active to not affect S3 power.
Signed-off-by: Pratik Vishwakarma
Reviewed
On 2020-10-29 12:31 a.m., Pratik Vishwakarma wrote:
[Why]
Incorrect values were resulting in flash lines
when MPO was enabled and system was left idle.
[How]
Increase min clk values only when MPO is enabled
and display is active to not affect S3 power.
Signed-off-by: Pratik Vishwakarma
Fine
Reviewed-by: Nicholas Kazlauskas
Looks fine to me. Feel free to apply.
Regards,
Nicholas Kazlauskas
On 2020-10-26 3:34 p.m., Alex Deucher wrote:
Yes, looks good to me as well. Series is:
Acked-by: Alex Deucher
I'll give the display guys a few more days to look this over, but if
there are no
On 2020-10-26 10:30 a.m., Alex Deucher wrote:
It looks this was accidently lost in a follow up patch.
dc context is large and we don't need contiguous pages.
Fixes: e4863f118a7d ("drm/amd/display: Multi display cause system lag on mode
change")
Signed-off-by: Alex Deucher
Cc: Aric Cyr
Cc: Ale
On 2020-10-21 7:31 p.m., Bas Nieuwenhuizen wrote:
Prepare for inserting modifiers based configuration, while sharing
a bunch of DCC validation & initializing the device-based configuration.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
On 2020-10-21 7:31 p.m., Bas Nieuwenhuizen wrote:
This moves the tiling_flags to the framebuffer creation.
This way the time of the "tiling" decision is the same as it
would be with modifiers.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
-
On 2020-10-21 7:31 p.m., Bas Nieuwenhuizen wrote:
With modifiers I'd like to support non-dedicated buffers for
images.
Signed-off-by: Bas Nieuwenhuizen
Cc: sta...@vger.kernel.org # 5.1.0
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu
On 2020-10-21 7:31 p.m., Bas Nieuwenhuizen wrote:
Otherwise the field ends up being used uninitialized when
enabling modifiers, failing validation with high likelyhood.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 2020-10-21 7:31 p.m., Bas Nieuwenhuizen wrote:
Silently accepting it could result in corruption.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
On 2020-10-15 11:02 p.m., Alex Deucher wrote:
On Wed, Oct 14, 2020 at 1:25 PM Andrey Grodzovsky
wrote:
On connector destruction call drm_dp_mst_topology_mgr_destroy
to release resources allocated in drm_dp_mst_topology_mgr_init.
Do it only if MST manager was initialized before otherwsie a cras
On 2020-10-14 9:20 a.m., Kazlauskas, Nicholas wrote:
On 2020-10-14 3:04 a.m., Yifan Zhang wrote:
Change-Id: I831a5ade8b87c23d21a63d08cc4d338468769e2b
Signed-off-by: Yifan Zhang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 61 +++
1 file changed, 61 insertions(+)
diff
On 2020-10-14 3:04 a.m., Yifan Zhang wrote:
Change-Id: I831a5ade8b87c23d21a63d08cc4d338468769e2b
Signed-off-by: Yifan Zhang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_d
On 2020-10-05 2:10 p.m., Bhawanpreet Lakha wrote:
These function pointers are missing from dcn30_init
.calc_vupdate_position
.set_pipe
So add them
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Nicholas Kazlauskas
Would be good to mention what these are used for specifically though.
The c
On 2020-10-01 5:06 a.m., Pratik Vishwakarma wrote:
[Why]
When overlay plane is in use and external display
is connected, atomic check will fail.
[How]
Disable overlay plane on multi-monitor scenario
by tying it to single crtc.
Signed-off-by: Pratik Vishwakarma
This will break overlay usage o
On 2020-09-28 3:31 p.m., Christian König wrote:
Am 28.09.20 um 19:35 schrieb James Ettle:
On Mon, 2020-09-28 at 10:26 -0400, Harry Wentland wrote:
On 2020-09-25 5:18 p.m., Alex Deucher wrote:
On Tue, Sep 22, 2020 at 4:51 PM James Ettle
wrote:
On 22/09/2020 21:33, Alex Deucher wrote:
+/**
+
On 2020-09-16 1:08 p.m., Bhawanpreet Lakha wrote:
[Why]
"Copy GSL groups when committing a new context" patch was accidentally
removed during a refactor
Patch: 21ffcc94d5b ("drm/amd/display: Copy GSL groups when committing a new
context")
[How]
Re add it
Fixes: b6e881c9474 ("drm/amd/display:
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