->state_array[i].phyclk_mhz = max_phyclk_mhz;
p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
Suggest code rework.
Regards
David Binderman
& (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced,
in this case, will have page fault within a group
IMHO, looks odd. Was && intended ?
Regards
David Binderman
lt;
optimal_dcfclk_for_uclk[j]) {
Regards
David Binderman
_uclk[j] && i <
num_dcfclk_sta_targets) {
It might be wise to move the limits check to before use.
Regards
David Binderman
- 1; j >= 0;
j--) {
but
unsigned int i, j, closest_clk_lvl;
so it looks like the loop never terminates. Suggest code rework.
Regards
David Binderman
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five bytes long. Suggest code rework.
Regards
David Binderman
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.
Regards
David Binderman
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dgpu_dpm_enable_uvd(adev, true);
else
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
So second function call never happens. Suggest code rework.
e_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
return false;
Suggest add some code to deal with the case that the for loop doesn't find
what it is looking for and so pipe_ctx is NULL.
Regards
David Binderman
in the same file:
[drivers/gpu/drm/radeon/r100.c:2550]: (style) Variable 'tmp' is assigned a value
that is never used.
[drivers/gpu/drm/radeon/r100.c:2875]: (style) Variable 'tmp' is assigned a value
that is never used.
Regards
David Binderman
r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
return 0;
Regards
David Binderman
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