On 7/9/25 13:56, Melissa Wen wrote:
No I think it will not work as expected for movable 3D LUT, since
movable 3D LUT is a MPC capability.
I have actually sent a patch in the past to clarify this on DCN401. So,
this check doesn't cover this driver anymore, for example.
- https://lore.kernel.o
Hi Simon,
It may be better to change it now if we know it needs changing in the
future.
Hi Xaver,
Do you think this need to be immutable or mutable? Do you believe this
need to be mutable?
On 7/9/25 14:30, Simon Ser wrote:
On Tuesday, June 17th, 2025 at 06:27, Alex Hung wrote:
- 1D
Thanks. I will send v6 to promotion test.
On 7/25/25 18:33, Melissa Wen wrote:
Hi,
Siqueira and I have been working on a solution to reduce the usage of
drm_edid_raw in the AMD display driver, since the current guideline in
the DRM subsystem is to stop handling raw edid data in driver-specific
This patch may be related and conflict to
https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg125873.html
amd-staging-drm-next should include the above patch but it is not
updated for 2 weeks, so let's wait for ASDN to be updated.
On 7/24/25 16:32, Rodrigo Siqueira wrote:
On 010/2
g
Between DIO/HPO")
Switching Between DIO/HPO")
Cc: Wayne Lin
Cc: George Shen
Cc: Michael Strauss
Cc: Mike Katsnelson
Cc: Alvin Lee
Cc: Ray Wu
Cc: Wenjing Liu
Cc: Harry Wentland
Cc: Tom Chung
Cc: Roman Li
Cc: Alex Hung
Cc: Aurabindo Pillai
Signed-off-by: Srinivasan Shanmugam
-
Reviewed-by: Alex Hung
On 7/21/25 07:22, Srinivasan Shanmugam wrote:
Fix the comment style before cntl_stuck_hw_workaround() by replacing
'/**' with '/*' since it is not a kdoc comment.
Fixes the below with gcc W=1:
display/dc/dce/dce_i2c_hw.c:380: warning: This comment st
Melisa,
The following NULL pointer error was reported from promotion test with
this patch:
[ 31.525028] amdgpu :c4:00.0: [drm] *ERROR* No EDID read.
[ 31.525596] amdgpu :c4:00.0: [drm:drm_dp_dpcd_read
[drm_display_helper]] AMDGPU DM aux hw bus 2: 0x6921d AUX -> (ret= 3)
00 00 0
r_caps'
Reviewed-by: Yihan Zhu
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 59c07756130d..fac976b2cbee 100644
--- a/drivers/gpu/drm/a
On 7/15/25 01:44, Shankar, Uma wrote:
-Original Message-
From: Borah, Chaitanya Kumar
Sent: Tuesday, July 15, 2025 10:08 AM
To: Alex Hung ; Simon Ser ;
Shankar, Uma
Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; wayland-
de...@lists.freedesktop.org
On 7/8/25 11:10, Simon Ser wrote:
On Tuesday, June 17th, 2025 at 06:26, Alex Hung wrote:
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 651bdf48b766..21bd96f437e0 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -872,6 +872,16
On 7/9/25 14:49, Borah, Chaitanya Kumar wrote:
Hi Alex,
-Original Message-
From: Alex Hung
Sent: Tuesday, June 17, 2025 9:47 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: wayland-de...@lists.freedesktop.org; harry.wentl...@amd.com;
alex.h...@amd.com; leo
Thanks Melissa. I will send this series to promotion test and post the
result by the end of next week.
On 6/18/25 11:19, Melissa Wen wrote:
Hi,
Siqueira and I have been working on a solution to reduce the usage of
drm_edid_raw in the AMD display driver, since the current guideline in
the DRM s
Reviewed-by: Alex Hung
On 6/23/25 11:11, Mario Limonciello wrote:
[Why]
Brightness programming may involve a conversion of a user requested
brightness against what was in a custom brightness curve. The values
might not match what a user programmed.
[How]
Add a new trace event to show specific
Hi,
Thanks for reporting. Can you please create a bug at
https://gitlab.freedesktop.org/drm/amd/-/issues/ for issue tracking and
log collection.
On 6/12/25 08:08, g...@tuxedocomputers.com wrote:
Hi,
I have discovered that two small form factor desktops with Ryzen AI 7
350 and Ryzen AI 5 340
We only create the DATA property for property types that
need it.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v9:
- Merge cleanup code for colorop->state->data in drm_c
colorop:
1. 1D curve colorop w/ sRGB EOTF
Signed-off-by: Alex Hung
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
V10:
- Replace DRM_ERROR by drm_err
- Creaet color pipeline when >= DCN_VERSION_3_0
V9:
- Update function names by _plane_ (Chaita
transfer function)
instead of as EOTF (electro-optical transfer function).
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Simon Ser
---
V9:
- Move DRM_COLOROP_1D_CURVE_BT2020_* from middle to end (Simon Ser)
drivers/gpu/drm/drm_colorop.c | 2
The functions are to clean up color pipeline when a device driver
fails to create its color pipeline.
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Simon Ser
Reviewed-by: Melissa Wen
---
v9:
- Move from from latest commit to here, and drm_colorop_pipeline_destroy
is
From: Harry Wentland
Not all HW will be able to do bypass on all color
operations. Introduce an 32 bits 'flags' for all colorop
init functions and DRM_COLOROP_FLAG_ALLOW_BYPASS for creating
the BYPASS property when it's true.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentla
er to allow for this we'll also invert the nesting of our
colorop processing loops. We now use the pixel iteration loop
on the outside and the colorop iteration on the inside.
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
From: Harry Wentland
Add kernel doc for AMD color pipeline.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 122 +++---
1 file changed, 102 insertions(+), 20 deletions
From: Harry Wentland
CTM values are defined as signed-magnitude values. Add
a helper that converts from CTM signed-magnitude fixed
point value to the twos-complement value used by
drm_fixed.
Reviewed-by: Louis Chauvet
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Meliss
From: Harry Wentland
Add the default Bypass pipeline and ensure it passes the
kms_colorop test plane-XR30-XR30-bypass.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
v10:
- guard "dm_plane_init_colorops" function when !AMD_PRIVATE_COLOR (M
Check dpp.hw_3d_lut before creating shaper tf/lut and 3dlut colorops in
colorpipeline and handling these colorops.
Signed-off-by: Alex Hung
---
V10:
- Check dpp.hw_3d_lut before creating shaper tf/lut and 3dlut colorops
(Melissa Wen)
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 47
The degamma is to be handled by Color pipeline API.
Signed-off-by: Alex Hung
---
V10:
- Disable CRTC degamma when color pipeline is enabled (Melissa Wen)
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a
This adds support for a 3D LUT.
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. Multiplier
3. 3x4 CTM
4. 1D curve colorop
5. 1D LUT
6. 3D LUT
7. 1D curve colorop
8. 1D LUT
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
---
V10:
- Support 32BIT RGB in 3D
It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.
new drm_colorop_type: DRM_COLOROP_3D_LUT.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
V10:
- Add missing set lut3d_interpolation
From: Harry Wentland
We want to make sure userspace is aware of the 1D LUT
interpolation. While linear interpolation is common it
might not be supported on all HW. Give driver implementers
a way to specify their interpolation.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by
Swap the order of matrix and multiplier as designed in hardware.
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
V9:
- Update function names by _plane_ (Chaitanya Kumar Borah)
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 12 ++--
.../drm/amd
This introduces a new drm_colorop_type: DRM_COLOROP_MULTIPLIER.
It's a simple multiplier to all pixel values. The value is
specified via a S31.32 fixed point provided via the
"MULTIPLIER" property.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Revie
colorops:
1. 1D curve colorop
2. 3x4 CTM
3. Multiplier
4. 1D curve colorop
5. 1D LUT
6. 1D curve colorop
7. 1D LUT
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
V10:
- Remove redundant DRM_ERROR(...)
V9:
- Update function names by _plane_ (Chaitanya Kumar Borah
-ctm_3x4_bt709_enc
kms_colorop --run plane-XR30-XR30-ctm_3x4_bt709_dec
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. 3x4 CTM
3. 1D curve colorop
4. 1D LUT
5. 1D curve colorop
6. 1D LUT
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel
colorops:
1. 1D curve colorop
2. 1D curve colorop
3. 1D LUT
4. 1D curve colorop
5. 1D LUT
The 1D curve colorops support sRGB, BT2020, and PQ scaled to 125.0.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
V10:
- Support 32BIT RGB in 1D LUT with
ch
is used by a driver to advertise the supported SIZE
of the LUT, as well as a DATA property which userspace
uses to set the LUT.
DATA and size function in the same way as current drm_crtc
GAMMA and DEGAMMA LUTs.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Co-developed-by: Harry Wentland
S
From: Uma Shankar
Existing LUT precision structure drm_color_lut has only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
Signed-off-by: Alex Hung
Signed-off-by: Uma Shankar
-bt2020_oetf
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
V10:
- Move amdgpu_dm_supported_*_tfs check to Patch 32 (Melissa Wen)
V9:
- Move DRM_COLOROP_1D_CURVE_BT2020_* from middle to end
v8:
- Move BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) in
plane-XR30-XR30-pq_125_inv_eotf
kms_colorop --run plane-XR30-XR30-pq_125_eotf-pq_125_inv_eotf
kms_colorop --run plane-XR30-XR30-pq_125_eotf-pq_125_inv_eotf-pq_125_eotf
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
V10:
- Move amdgpu_dm_supported_*_tfs check
eason AMD HW hard-codes a PQ
function that is scaled by 125, yielding 80 nit PQ values for
1.0 and 10,000 nits at 125.0.
This patch introduces this scaled PQ EOTF and its inverse as
1D curve types.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel
pipeline now consists of the following colorops:
1. 1D curve colorop w/ sRGB EOTF support
2. 1D curve colorop w/ sRGB Inverse EOTF support
3. 1D curve colorop w/ sRGB EOTF support
Signed-off-by: Alex Hung
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
-XR30-XR30-srgb_eotf-srgb_inv_eotf
The color pipeline now consists of the following colorops:
1. 1D curve colorop w/ sRGB EOTF support
2. 1D curve colorop w/ sRGB Inverse EOTF support
Signed-off-by: Alex Hung
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Reviewed-by: Daniel
cursor plane does not need to have color pipeline.
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v7:
- Add a commit messages
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd
From: Harry Wentland
When the plane_color_pipeline bit is set we should ignore
deprecated properties, such as COLOR_RANGE and COLOR_ENCODING.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm
Create a new macro for_each_new_colorop_in_state to access new
drm_colorop_state updated from uapi.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v10:
- remove duplicated "is useful" in comments
include/drm/drm_ato
: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v5:
- Fix kernel docs
drivers/gpu/drm/drm_atomic_uapi.c | 1 +
include/drm/drm_atomic.h | 18 ++
2 files changed, 19 insertions(+)
diff --git a
From: Harry Wentland
A whole slew of tests for CTM handling that greatly helped in
debugging the CTM code. The extent of tests might seem a bit
silly but they're fast and might someday help save someone
else's day when debugging this.
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hu
dding the
drm_test_int2fixp test that validates the above assumption.
I am also adding a test for the new sm2fixp function that converts
from a signed-magnitude fixed point to the twos-complement fixed
point.
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Review
that the matrix entries are in signed-magnitude fixed
point, whereas the drm_fixed.h implementation uses 2s-complement.
The latter one is the one that we want for easy addition and
subtraction, so we convert all entries to 2s-complement.
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signe
From: Harry Wentland
Two tests are added to VKMS LUT handling:
- linear
- inv_srgb
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
v7:
- Fix checkpatch warnings (Louis Chauvet)
- Adde a commit messages
- Fix code styles by
hout clear indication
that we need it. We'll revisit and, if necessary, regenerate
the LUTs when we have IGT tests for higher precision buffers.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
---
V9:
- Replace cleanup code by drm_colorop_pipeline_des
d for userspace that sets this
client cap.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
V9:
- Fix typo in commit description (Shengyu Qu)
v8:
- Disallow setting of COLOR_RANGE and COLOR_ENCODING
From: Harry Wentland
Add kernel doc for drm_colorop objects.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v8:
- Move this after "drm/colorop: Introduce DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE"
color
pipelines, as well as set the desired one. The color
pipelines are programmed via properties on the actual
drm_colorop objects.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
V9:
- Remove redundant com
From: Harry Wentland
We'll construct color pipelines out of drm_colorop by
chaining them via the NEXT pointer. NEXT will point to
the next drm_colorop in the pipeline, or by 0 if we're
at the end of the pipeline.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harr
From: Harry Wentland
Print atomic state for drm_colorop in debugfs
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v8:
- Add switch statement to print colorop type (Simon Ser)
v7:
- Add a commit
From: Harry Wentland
Add a new drm_colorop with DRM_COLOROP_1D_CURVE with two subtypes:
DRM_COLOROP_1D_CURVE_SRGB_EOTF and DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-off-by: Harry Wentland
Co-developed-by: Alex Hung
Signed-off-by: Alex Hung
From: Harry Wentland
We want to be able to bypass each colorop at all times.
Introduce a new BYPASS boolean property for this.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v6
igned-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v6:
- fix doc typo (Alex Hung)
v5:
- Add drm_get_colorop_type_name in header
- Add kernel docs
v4:
- Use enum property for TYPE (Pekka)
v3:
- Make TYPE a range property
- Move
-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v8:
- Remove drm_atomic_get_existing_colorop_state (Louis Chauvet)
v7:
- Fix checkpatch warnings and errors
- Add a tab to for_each_oldnew_colorop_in_state definition
- Change unsigned
From: Harry Wentland
Add documentation for color pipeline API.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Simon Ser
Reviewed-by: Melissa Wen
---
V9:
- Update documents according to new 3DLUT changes (Simon Ser)
- Spell out the behaviours
From: Harry Wentland
Debugging LUT math is much easier when we can unit test
it. Add kunit functionality to VKMS and add tests for
- get_lut_index
- lerp_u16
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Cc: Arthur Grillo
Reviewed-by: Daniel Stone
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Jonas Ådahl
Cc: Sebastian Wick
Cc: Shashank Sharma
Cc: Alexander Goins
Cc: Joshua Ashton
Cc: Michel Dänzer
Cc: Aleix Pol
Cc: Xaver Hugl
Cc: Victoria Brekenfeld
Cc: Sima
Cc: Uma Shankar
Cc: Naseer Ahmed
Cc: Christopher Braga
Cc: Abhinav Kumar
C
On 6/10/25 00:10, Markus Elfring wrote:
From: Markus Elfring
Date: Tue, 10 Jun 2025 07:42:40 +0200
The label “cleanup” was used to jump to another pointer check despite of
the detail in the implementation of the function
“dm_validate_stream_and_context”
that it was determined already that c
Reviewed-by: Alex Hung
This patchset passed promotion tests along with DC 3.2.337 too.
On 6/1/25 19:44, Mario Limonciello wrote:
From: Mario Limonciello
Chris Bainbridge reported some list corruption occurring around the
suspend sequence when an aborted suspend occurs.
I couldn't repr
From: Yihan Zhu
[WHY & HOW]
Fix RMCM programming sequence errors and mapping issues to pass the RMCM
test.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Dmytro Laktyushkin
Signed-off-by: Yihan Zhu
Signed-off-by: Alex Hung
---
.../dc/dml2/dml21
From: Dillon Varone
[WHY & HOW]
DCN401 is only supported using DML2.1, so remove unused code and files.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Alex Hung
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 67 +++--
drivers/gpu/drm/amd/display/dc/dml/Make
:
Create a flattened struct containing all sensitive parameters in the
bounding box. New parameters can be added to the bottom of the new struct
as needed.
Reviewed-by: Dillon Varone
Signed-off-by: Austin Zheng
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
From: Ryan Seto
[WHY & HOW]
Clear DPP 3DLUT Cap flag on ASICs that do not use it
Reviewed-by: Alvin Lee
Signed-off-by: Ryan Seto
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
because these are in 0-0xFF range. Advertise full
PWM range to userspace.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Roman Li
Signed-off-by: Mario Limonciello
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 ---
1
eling
- Remove dpia debug bits
Signed-off-by: Taimur Hassan
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 74379edcc4b1..da024b0d0eba 1
27;mpc_color_caps'
./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter
or struct member 'rmcm_3d_lut_caps' not described in 'mpc_color_caps'
./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter
or struct member 'preblend' not describe
: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Roman Li
Signed-off-by: Mario Limonciello
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
From: Yihan Zhu
[WHY & HOW]
Add new FL feature debug logging into the existing DTN logging.
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Signed-off-by: Yihan Zhu
Signed-off-by: Alex Hung
---
.../amd/display/dc/hubp/dcn10/dcn10_hubp.h| 19 ++
.../amd/display/dc/
Cc: sta...@vger.kernel.org
Reviewed-by: Harry Wentland
Reviewed-by: Austin Zheng
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 1 +
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c| 1 +
2 files changed, 2 insertions(+)
diff
From: Aurabindo Pillai
* Add a missing compilation unit
* Missing CFLAGS for certain units
Reviewed-by: Roman Li
Signed-off-by: Aurabindo Pillai
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml2/Makefile| 13 +++--
.../dc/dml2/dml21/src/dml2_core
From: Ausef Yousof
[WHY & HOW]
Unnecessary to affect legacy APU's dto src sel during dpms behaviour
Reviewed-by: Charlene Liu
Signed-off-by: Ausef Yousof
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/h
From: Muhammad Ahmed
[WHY]
On some 8k display models flickering or black screens may occur at reduced
PHY SSC.
[HOW]
Add an option to set a workaround bit for these displays to keep the old
SSC value.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Muhammad Ahmed
Signed-off-by: Alex Hung
from OS during dpms off. will scope out dcn315 as it was
affecting diags tests on certain CI machines (not crbs)
Reviewed-by: Leo Chen
Signed-off-by: Ausef Yousof
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c| 6 --
drivers/gpu/drm/amd/display/dc/
Steve Leder
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c| 17 +++--
.../gpu/drm/amd/display/dc/sspl/dc_spl_types.h | 2 ++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c
b/drivers/gpu/drm
From: Dmytro Laktyushkin
[WHAT]
Update tmz_surface's type to match register size
Reviewed-by: Charlene Liu
Signed-off-by: Dmytro Laktyushkin
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dr
t the HUBP domain matching the DSC instance
is appropriately powered.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Duncan Ma
Signed-off-by: Nicholas Kazlauskas
Signed-off-by: Alex Hung
---
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 28 +
From: Dillon Varone
[WHY & HOW]
Use a dedicated DC power option and instance pair.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Alex Hung
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 20 +++
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h
added helper function to
calculate the correct DPCD address to target potentially embedded LTTPRs
based on the received LTTPR count.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Wenjing Liu
Signed-off-by: Michael Strauss
Signed-off-by: Alex Hung
---
drivers/gp
From: Charlene Liu
[WHAT]
Add HW change to required mpc gamut remap
Reviewed-by: Dmytro Laktyushkin
Signed-off-by: Charlene Liu
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h| 3 ++-
.../gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c | 10
From: Cruise Hung
[WHY & HOW]
The BW zero allocation patch is no longer required.
Add a debug option to enable it in case we encounter an issue.
Reviewed-by: Wenjing Liu
Signed-off-by: Cruise Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc.h| 3 ++-
..
From: Peichen Huang
[WHAT]
1. add dc cap for dp tunneling
2. add function to get index of host router
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Cruise Hung
Signed-off-by: Peichen Huang
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core
From: Peichen Huang
[WHY]
Remove some unused dpia debug bits.
[HOW]
Remove them from dpia_debug_options.
Reviewed-by: Cruise Hung
Reviewed-by: Robin Chen
Signed-off-by: Peichen Huang
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc.h | 5 +
1 file changed, 1 insertion
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements on DCN4, MPC, DSC, DP and others
* Enhancements on backlight and brightness
* Fixes on mpv video playback and display flicking
Cc: Daniel Wheeler
Alex Hung (2):
drm/amd/display: Fix mpv playback
There is a work-in-progress supplement patch. Let's wait and see whether
it fixes the regressions without reverting 46e68dd5066c.
On 5/27/25 11:06, Alex Hung wrote:
This reverts commit 46e68dd5066c9831e9695c1756db017bb9c3762c since it
breaks color enhancement in another OS, indicating
This reverts commit 46e68dd5066c9831e9695c1756db017bb9c3762c since it
breaks color enhancement in another OS, indicating these two fields are
still used by color management in dcn401.
Fixes: 46e68dd5066c ("drm/amd/display: no 3D and blnd LUT as DPP color caps for
DCN401")
Signed-of
Hi Leonardo,
Thank you for this patch, but unfortunately some unit test suites depend
on the names.
On 5/21/25 07:58, Leonardo Gomes wrote:
From: Leonardo da Silva Gomes
Adjust the dcn31_apg construct function name from
'apg31_construct' to 'dcn31_apg_construct'.
This helps the ftrace to de
Reviewed-by: Alex Hung
On 5/24/25 10:51, Christophe JAILLET wrote:
'struct timing_generator_funcs' are not modified in these drivers.
Constifying these structures moves some data to a read-only section, so
increases overall security, especially when the structure holds some
functio
Reviewed-by: Alex Hung
On 5/25/25 20:37, Wentao Liang wrote:
The function mod_hdcp_hdcp1_enable_encryption() calls the function
get_first_active_display(), but does not check its return value.
The return value is a null pointer if the display list is empty.
This will lead to a null pointer
Reviewed-by: Alex Hung
On 4/29/25 16:39, Melissa Wen wrote:
On 25/04/2025 17:52, Melissa Wen wrote:
Match what is declared as DPP color caps with hw caps. DCN401 has MPC
shaper+3D+blnd LUTs that are movable before and after blending (get from
plane or stream), but no DPP shaper+3D+blend
Reviewed-by: Alex Hung
On 5/13/25 15:38, Melissa Wen wrote:
Color gamut_remap state log may be not avaiable for some hw versions, so
prevent null pointer dereference by checking if there is a function to
collect data for this hw version.
v2:
- initialize is_gamut_remap_available (Alex H
On 5/19/25 20:06, James wrote:
On Mon, May 5, 2025, at 9:02 AM, Alex Hung wrote:
Reviewed-by: Alex Hung
On 5/3/25 15:18, James Flowers wrote:
Adds kernel-doc for externally linked dc_stream_remove_writeback function.
Signed-off-by: James Flowers
---
V1 -> V2: Corrected checkpa
On 4/25/25 14:49, Melissa Wen wrote:
Color gamut_remap state log may be not avaiable for some hw versions, so
prevent null pointer dereference by checking it there is a function to
collect data for this hw version.
Signed-off-by: Melissa Wen
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c
Reviewed-by: Alex Hung
On 4/22/25 08:58, Melissa Wen wrote:
This reverts commit 272e6aab14bbf98d7a06b2b1cd6308a02d4a10a1.
Applying degamma curve to the cursor by default breaks Linux userspace
expectation.
On Linux, AMD display manager enables cursor degamma ROM just for
implict sRGB on HW
On 4/25/25 07:50, Leandro Ribeiro wrote:
On 3/26/25 20:47, Alex Hung wrote:
It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.
new drm_colorop_type: DRM_COLOROP_3D_LUT.
Signed-off-by: Alex Hung
---
v8:
- Fix typo in subject (Simon
On 5/12/25 18:52, Melissa Wen wrote:
On 04/29, Alex Hung wrote:
This adds support for a 3D LUT.
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. Multiplier
3. 3x4 CTM
4. 1D curve colorop
5. 1D LUT
6. 3D LUT
7. 1D curve colorop
8. 1D LUT
Signed-off-by: Alex
Hi Melissa,
The patchset looks good to me but there is WIP dcn401 code, meaning
dcn20 and dcn401 are different.
I will check how to refactor code so this patchset can fit better.
Thanks
On 4/30/25 08:20, Melissa Wen wrote:
Hi,
I've been examining dcn401 code to figure out what is causing a
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