Le 15/04/2025 à 21:54, jim.cro...@gmail.com a écrit :
On Tue, Apr 15, 2025 at 4:04 AM Louis Chauvet wrote:
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Add __DYNAMIC_DEBUG_CLASSMAP_CHECK to implement the following
arg-checks at compile-time:
0 <= _base < 63
class_names is n
Add and expose board voltage node as vddboard to hwmon for smu_v13_0_6
v2: Replace ip check with supported sensor attribute(Lijo)
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 34 +
Fill static metrics data for smu_v13_0_6
v2: Proceed with driver load just with warning even if board
voltage reads invalid value
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 +
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c |
Add & enable board voltage caps for smu_v13_0_6
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/
Use common function to fetch static metrics table for smu_v13_0_12
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 22 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h |
Fetch static metrics table for smu_v13_0_6
v2: Add static metrics caps check to fetch static metrics table
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28 +++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/dr
Update pmfw headers for smu_v_13_0_6 to include static metrics table
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h| 7 +++
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
2 files changed, 9 insertions(+)
Add ip version check to use smu_v13_0_12 specific functions
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.
On 4/15/2025 7:53 PM, Christian König wrote:
Am 15.04.25 um 16:18 schrieb Arvind Yadav:
Mesa passes shared bo, fence syncobj to userq_ioctl.
There can be duplicates here or some fences that are old.
This patch is remove duplicates fence and only keep
the most recent fence for each context.
Cc
When peer memory is accessed through XGMI, it does not need to be visible
in the BAR and there is no need for SG-tables or DMA mappings.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --gi
If peer memory is accessible through XGMI, allow leaving it in VRAM
rather than forcing its migration to GTT on DMABuf attachment.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 31 -
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git
Pinning of VRAM is for peer devices that don't support dynamic attachment
and move notifiers. But it requires that all such peer devices are able to
access VRAM via PCIe P2P. Any device without P2P access requires migration
to GTT, which fails if the memory is already pinned for another peer
device
Hi all,
Friendly ping (second one): who can take this patch, please? 🙂
Thanks!
-Gustavo
On 11/03/25 02:10, Gustavo A. R. Silva wrote:
Hi all,
Friendly ping: who can take this, please? :)
Thanks!
--
Gustavo
On 14/02/25 18:48, Gustavo A. R. Silva wrote:
-Wflex-array-member-not-at-end was int
add process and pid information in the userqueue error
logging to make it more useful in resolving the error
by logs.
Sample log:
[ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
out waiting for fence f=1c74d978 for comm:Xwayland pid:3427
[ 42.444669] [drm:am
drm_file will be used in usermode queues code to
enable better process information in logging and hence
add drm_file part of the userq_mgr struct.
update the drm_file pointer in userq_mgr for each
amdgpu_driver_open_kms.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
change the DRM_ERROR to drm_file_err which gives the drm device
information too which is useful in case of multiple GPU's and also
add process information.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 59 +++
1 file changed, 33 insertions(+), 26
Add a drm helper function which get the process information for
the drm_file and append the process information using the existing
drm_err.
Signed-off-by: Sunil Khatri
---
include/drm/drm_file.h | 40
1 file changed, 40 insertions(+)
diff --git a/include
Functionally code looks good to me for the intended purposes
Reviewed-by: Sunil Khatri
On 4/14/2025 11:52 PM, Alex Deucher wrote:
Replace disable_kq parameter with user_queue parameter.
The parameter has the following logic:
-1 = auto (ASIC specific default)
0 = user queues disabled
1 =
Thanks for the fix, I had the same patch submitted yesterday.
Regards,
Eric
On 2025-04-15 06:44, Dan Carpenter wrote:
The "pdd->drm_priv" NULL check is reversed so it will lead to a NULL
dereference on the next line.
Fixes: 4172b556fd5b ("drm/amdkfd: add smi events for process start and end")
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Remove the DD_CLASS_TYPE_*_NAMES classmap types and code.
These 2 classmap types accept class names at the PARAM interface, for
example:
echo +DRM_UT_CORE,-DRM_UT_KMS > /sys/module/drm/parameters/debug_names
The code works, but its only used by
On Mon, Apr 14, 2025 at 9:32 PM Emily Deng wrote:
>
> For VF, it doesn't have the permission to clear overflow, clear the bit
> by reset.
>
> Signed-off-by: Emily Deng
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 15 +--
> drivers/gpu/drm/amd/amdgpu/amdg
Fill static metrics data for smu_v13_0_6
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/sws
On Tuesday, April 15th, 2025 at 17:05, Harry Wentland
wrote:
> > > > We want to have just one change in the way we expose the hardware
> > > > capabilities else all looks good in general.
> > >
> > > I would really recommend leaving this as a follow-up extension. It's a
> > > complicated
> > >
Add & enable board voltage caps for smu_v13_0_6
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/
From: Automatic Promotion
Summary:
* Implement HDMI Read request
* RMCM and MCM 3DLUT support
* Enable urgent latency adjustment on DCN35
* Enable phy-ssc reduction by default
Signed-off-by: Taimur Hassan
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file cha
From: Meenakshikumar Somasundaram
[Why]
Pixel rate dividor was not programmed correctly for 1 pixel per cycle
configuration for empty tu case.
[How]
Included check for empty tu when pixel rate dividor values were selected.
Reviewed-by: Michael Strauss
Signed-off-by: Meenakshikumar Somasundaram
This DC patchset brings improvements in multiple areas. In summary, we have:
- Implement HDMI Read request
- RMCM and MCM 3DLUT support
- Enable urgent latency adjustment on DCN35
- Enable phy-ssc reduction by default
- Use 16ms AUX read interval for LTTPR with old sinks
- Init DCN35 clocks from
On 14/04/2025 18:58, Christian König wrote:
Adding Pierre-eric and Tvrtko as well.
Thanks!
Am 11.04.25 um 15:04 schrieb Sunil Khatri:
Add helper function which get the process information for
the drm_file and updates the user provided character buffer
with the information of process name a
From: Leo Li
[Why]
Recent findings show negligible power savings between IPS2 and RCG
during static desktop. In fact, DCN related clocks are higher
when IPS2 is enabled vs RCG.
RCG_IN_ACTIVE is also the default policy for another OS supported by
DC, and it has faster entry/exit.
[How]
Remove
From: George Shen
[Why/How]
LTTPR are required to program DPCD Eh to 0x4 (16ms) upon AUX read
reply to this register. Since old Sinks witih DPCD rev 1.1 and earlier
may not support this register, assume the mandatory value is programmed
by the LTTPR to avoid AUX timeout issues.
Reviewed-by:
From: Leo Li
[Why]
We did not initialize dc clocks with boot-time hw values during init.
This lead to incorrect clock values in dc, causing `dcn35_update_clocks`
to make incorrect updates.
DCN35+ also allows 0 dtbclk -- current dm_init policy disallows it.
[How]
Correctly initialize DC with p
From: Austin Zheng
[Why]
Large stack size observed in DCN4 mode support when compiling with clang.
Additional instrumentation added by compiler adds to stack size.
dml_core_mode_support ends up going over the stack size limit
due to the size of the function.
[How]
Move checks and calculations fo
From: TungYu Lu
[Why]
The minimum value of the dst_y_prefetch_equ was not correct
in prefetch calculation whice causes OPTC underflow.
[How]
Add the min operation of dst_y_prefetch_equ in prefetch calculation
for legacy DML.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: TungYu Lu
Signed-off
From: Gergo Koteles
Since b255ce4388e0, it is possible that the CRTC timing
information for the preferred mode has not yet been
calculated while amdgpu_dm_connector_mode_valid() is running.
In this case use the CRTC timing information of the actual mode.
Fixes: b255ce4388e0 ("drm/amdgpu: don't
From: Roman Li
[Why]
Reduction of phy-ssc is needed to support DP2 high pixel clock on dcn35x/36.
There's a special flag to enable it in dmub hw params.
[How]
Set hbr3_phy_ssc to true for dcn35, dcn351 and dcn36.
Reviewed-by: Charlene Liu
Signed-off-by: Roman Li
Signed-off-by: Zaeem Mohamed
From: Chris Park
[Why]
Read Request provides alterative method to polling to
the HDMI sinks that support it.
[How]
Implement Read Request where interrupt can be generated
by the sink.
Reviewed-by: Joshua Aberback
Signed-off-by: Chris Park
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd
On 4/15/2025 5:42 PM, Christian König wrote:
This reverts commit c2cc3648ba517a6c270500b5447d5a1efdad5936. Turned out
that this has some negative consequences for some workloads. Instead check
if the cleaner shader should run directly.
While at it remove amdgpu_vm_need_pipeline_sync(), we also
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
If a module _DEFINEs + _USEs 2 or more classmaps, it must devise them
to share the per-module 0..62 class-id space; ie their respective
base,+length reservations cannot overlap.
To detect conflicts at modprobe, add ddebug_class_range_overlap(),
call
> The return value of fiji_populate_smc_boot_level() is needs to be checked.
should?
> An error handling is also needed to phm_find_boot_level() to reset the
> boot level when the function fails. A proper implementation can be found
> in tonga
From: Jay Cornwall
[ Upstream commit 3666ed821832f42baaf25f362680dda603cde732 ]
KIQ invalidate_tlbs request has been seen to marginally exceed the
configured 100 ms timeout on systems under load.
All other KIQ requests in the driver use a 10 second timeout. Use a
similar timeout implementation
On 4/14/2025 9:02 PM, Alex Deucher wrote:
On Mon, Apr 14, 2025 at 5:59 AM Khatri, Sunil wrote:
Same explanation as patch 1 of the series here too. Do we want to depend
on the disable_kq flag solely to enable/disable sdma trap.
IIUC, we dont want to do it in case of kernel queues at all and on
On 04/13, Alex Deucher wrote:
> On Sat, Apr 12, 2025 at 4:22 PM Rodrigo Siqueira wrote:
> >
> > CHIP_KAVERI, CHIP_KABINI, and CHIP_MULLINS have the same buffer
> > manipulation as the default option in the switch case. Remove those
> > specific manipulations and rely on the default behavior for th
Am 15.04.25 um 13:40 schrieb Tvrtko Ursulin:
>
> On 15/04/2025 12:25, Sunil Khatri wrote:
>> Add helper function which get the process information for
>> the drm_file and updates the user provided character buffer
>> with the information of process name and pid as a string.
>>
>> Signed-off-by: Sun
From: Dillon Varone
[WHY]
There are several gaps that can result in SubVP being enabled with
incompatible HW cursor sizes, and unjust restrictions to cursor size due
to wrong predictions on future usage of SubVP.
[HOW]
- remove "prediction" logic in favor of tagging based on previous SubVP
usa
On 2025-04-10 03:53, Pekka Paalanen wrote:
> On Tue, 8 Apr 2025 13:30:46 -0400
> Harry Wentland wrote:
>
>> On 2025-04-08 12:40, Daniel Stone wrote:
>>> Hi there,
>>>
>>> On Tue, 1 Apr 2025 at 20:53, Simon Ser wrote:
On Tuesday, April 1st, 2025 at 17:14, Daniel Stone
wrote:
>
Add ip version check to use smu_v13_0_12 specific functions
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.
Fetch static metrics table for smu_v13_0_6
v2: Add static metrics caps check to fetch static metrics table
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28 +++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/dr
On 2025-04-15 02:40, Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Simon Ser
>> Sent: Tuesday, April 15, 2025 11:47 AM
>> To: Shankar, Uma
>> Cc: Alex Hung ; dri-de...@lists.freedesktop.org; amd-
>> g...@lists.freedesktop.org; intel-...@lists.freedesktop.org; wayland-
>> de.
Am 15.04.25 um 16:18 schrieb Arvind Yadav:
> Mesa passes shared bo, fence syncobj to userq_ioctl.
> There can be duplicates here or some fences that are old.
> This patch is remove duplicates fence and only keep
> the most recent fence for each context.
>
> Cc: Alex Deucher
> Cc: Christian König
From: Mario Limonciello
[Why]
The ACPI EDID in the BIOS of a Lenovo laptop includes 3 blocks, but
dm_helpers_probe_acpi_edid() has a start that is 'char'. The 3rd
block index starts after 255, so it can't be indexed properly.
This leads to problems with the display when the EDID is parsed.
[How
From: Charlene Liu
[why]
not all the asic using the same code path.
need to revisit and limit the impact.
This reverts commit 075634792e54ef201cbbdf0422c077b8724b907.
Reviewed-by: Gabe Teeger
Signed-off-by: Charlene Liu
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/hwss/dc
From: Yihan Zhu
[WHY & HOW]
Providing hardware programming for the RMCM and MCM IPs for 3DLUT in DCN42.
Reviewed-by: Charlene Liu
Signed-off-by: Yihan Zhu
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 9 +-
.../dc/dml2/dml21/dml21_translation_helper.c |
From: Nicholas Susanto
[Why]
Urgent latency adjustment was disabled on DCN35 due to issues with P0
enablement on some platforms. Without urgent latency, underflows occur
when doing certain high timing configurations. After testing, we found
that reenabling urgent latency didn't reintroduce p0 su
From: Aurabindo Pillai
When userspace asks us to enable vblank on a crtc that is not yet
enabled return -EINVAL. There is no need to queue the vblank handler in
this case, so return early.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1856
Reviewed-by: Sun peng Li
Signed-off-by: Aura
From: Jack Chang
[Why & How]
Move desync error counter operation up to prevent
it from being skipped by force disable desync
error.
Reviewed-by: Robin Chen
Reviewed-by: Aric Cyr
Signed-off-by: Jack Chang
Signed-off-by: Zaeem Mohamed
---
.../amd/display/dc/link/protocols/link_dp_irq_handler.
From: Roman Li
[Why]
While system undergoing gpu reset always do full update
to sync the dc state before and after reset.
[How]
Return true in should_reset_plane() if gpu reset detected
Cc:
Reviewed-by: Aurabindo Pillai
Reviewed-by: Mario Limonciello
Signed-off-by: Roman Li
Signed-off-by:
From: Roman Li
[Why]
The indexing of stream_status in dm_gpureset_commit_state() is incorrect.
That leads to asserts in multi-display configuration after gpu reset.
[How]
Adjust the indexing logic to align stream_status with surface_updates.
Fixes: cdaae8371aa9 ("drm/amd/display: Handle GPU res
From: Yihan Zhu
[WHY & HOW]
Avoid null curve data structure used in the cm block for the potential issue.
Reviewed-by: Charlene Liu
Signed-off-by: Yihan Zhu
Signed-off-by: Zaeem Mohamed
---
.../drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 380 +-
1 file changed, 192 insertions
From: yi-lchen
[Why]
For some pixel clock margin sensitive external monitor,
we could not keep original DP ref clock for the ASICs
supported SSC DP ref clock.
[How]
>From slicon design team's comment,
we have to apply the adjusted DP ref clock for
DP devices.
DP 128b (DP2) signals uses the DTBCL
From: Mario Limonciello
[Why]
If the dummy values in `populate_dummy_dml_surface_cfg()` aren't updated
then they can lead to a divide by zero in downstream callers like
CalculateVMAndRowBytes()
[How]
Initialize dummy value to a value to avoid divide by zero.
Reviewed-by: Alex Hung
Signed-off-b
Mesa passes shared bo, fence syncobj to userq_ioctl.
There can be duplicates here or some fences that are old.
This patch is remove duplicates fence and only keep
the most recent fence for each context.
Cc: Alex Deucher
Cc: Christian König
Cc: Sunil Khatri
Cc: Arunpravin Paneer Selvam
Signed-o
On 4/15/2025 5:10 PM, Tvrtko Ursulin wrote:
On 15/04/2025 12:25, Sunil Khatri wrote:
Add helper function which get the process information for
the drm_file and updates the user provided character buffer
with the information of process name and pid as a string.
Signed-off-by: Sunil Khatri
--
Add and expose board voltage node as vddboard to hwmon for smu_v13_0_6
v2: Replace ip check with supported sensor attribute(Lijo)
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 34 +
Use common function to fetch static metrics table for smu_v13_0_12
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 22 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h |
Update pmfw headers for smu_v_13_0_6 to include static metrics table
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h| 7 +++
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
2 files changed, 9 insertions(+)
change the DRM_ERROR to drm_err which gives the drm device
information too which is useful in case of multiple GPU's.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 75 ++-
1 file changed, 41 insertions(+), 34 deletions(-)
diff --git a/drivers/gp
On 4/15/2025 12:50 AM, Alex Deucher wrote:
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
v2: split out v
The "pdd->drm_priv" NULL check is reversed so it will lead to a NULL
dereference on the next line.
Fixes: 4172b556fd5b ("drm/amdkfd: add smi events for process start and end")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 2 +-
1 file changed, 1 insertion(+), 1 d
In vegam_populate_smc_boot_level(), the return value of
phm_find_boot_level() is 0 or negative error code and the
"if (result)" branch statement will never run into the true
branch. Besides, this will skip setting the voltages later
below. Returning early may break working devices.
Add an error ha
Am 15.04.25 um 13:25 schrieb Sunil Khatri:
> Add helper function which get the process information for
> the drm_file and updates the user provided character buffer
> with the information of process name and pid as a string.
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/drm_file.c | 34
This reverts commit c2cc3648ba517a6c270500b5447d5a1efdad5936. Turned out
that this has some negative consequences for some workloads. Instead check
if the cleaner shader should run directly.
While at it remove amdgpu_vm_need_pipeline_sync(), we also check again
if the VMID has seen a GPU reset sin
On 15/04/2025 12:25, Sunil Khatri wrote:
Add helper function which get the process information for
the drm_file and updates the user provided character buffer
with the information of process name and pid as a string.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/drm_file.c | 34 ++
drm_file will be used in usermode queues code to
enable better process information in logging and hence
add drm_file part of the userq_mgr struct.
update the drm_file pointer in userq_mgr for each
amdgpu_driver_open_kms.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
Add helper function which get the process information for
the drm_file and updates the user provided character buffer
with the information of process name and pid as a string.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/drm_file.c | 34 ++
include/drm/drm_file
add process and pid information in the userqueue error
logging to make it more useful in resolving the error
by logs.
Sample log:
[ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
out waiting for fence f=1c74d978 for comm:Xwayland pid:3427
[ 42.444669] [drm:am
On 4/8/2025 10:10 PM, Daniel Stone wrote:
As it stands, I've gone through the implementation pretty thoroughly,
as well as our use of it in Weston. I'm happy with how it looks for
pre-blend, and I'm even happier that the implementation is written to
apply easily to apply to post-blend CRTC pip
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
echo 1000 > /sys/module/test_dynamic_debug/parameters/do_prints
This allows its use as a scriptable load generator, to generate
dynamic-prefix-emits for flag combinations vs undecorated messages.
This will make it easy to assess the cost of the pref
Hi Melissa,
kernel test robot noticed the following build warnings:
[auto build test WARNING on amd-pstate/linux-next]
[also build test WARNING on amd-pstate/bleeding-edge linus/master v6.15-rc2
next-20250415]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
The return value of fiji_populate_smc_boot_level() is needs to be checked.
An error handling is also needed to phm_find_boot_level() to reset the
boot level when the function fails. A proper implementation can be found
in tonga_populate_smc_boot_level().
Fixes: dcaf3483ae46 ("drm/amd/pm/powerplay/
On Wed, 2025-04-09 at 16:04 +0200, Philipp Stanner wrote:
> +Cc Matthew
>
> On Wed, 2025-04-09 at 15:55 +0200, Christian König wrote:
> > Am 09.04.25 um 12:28 schrieb Philipp Stanner:
> > > On Fri, 2025-03-21 at 16:58 +0100, Christian König wrote:
> > > > Sometimes drivers need to be able to submi
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Current classmap code protects class'd pr_debugs from unintended
changes by "legacy" unclassed queries:
# this doesn't disable all of DRM_UT_* categories
echo "-p" > /proc/dynamic_debug/control
# name the class to change it - protective bu
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
move the DYNAMIC_DEBUG_CLASSMAP_PARAM macro from test-dynamic-debug.c into
the header, and refine it, by distinguishing the 2 use cases:
1.DYNAMIC_DEBUG_CLASSMAP_PARAM_REF
for DRM, to pass in extern __drm_debug by name.
dyndbg keeps bits i
On 4/15/2025 2:14 PM, Tvrtko Ursulin wrote:
On 14/04/2025 18:58, Christian König wrote:
Adding Pierre-eric and Tvrtko as well.
Thanks!
Am 11.04.25 um 15:04 schrieb Sunil Khatri:
Add helper function which get the process information for
the drm_file and updates the user provided character
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Describe the 3 API macros providing dynamic_debug's classmaps
DYNDBG_CLASSMAP_DEFINE - create & export a classmap
DYNDBG_CLASSMAP_USE- refer to exported map
DYNDBG_CLASSMAP_PARAM - bind control param to the classmap
DYNDBG_CLASSMAP_PARAM_REF +
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
The Xe driver's XE_IOCTL_DBG macro calls drm_dbg() from inside an if
(expression). This breaks when CONFIG_DRM_USE_DYNAMIC_DEBUG=y because
the invoked macro has a do-while-0 wrapper.
if (cond && (drm_dbg("expr-form"),1)) {
... do some mo
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Treat comma as a token terminator, just like a space. This allows a
user to avoid quoting hassles when spaces are otherwise needed:
:#> modprobe drm dyndbg=class,DRM_UT_CORE,+p\;class,DRM_UT_KMS,+p
or as a boot arg:
drm.dyndbg=class,DRM_UT_CO
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Add __DYNAMIC_DEBUG_CLASSMAP_CHECK to implement the following
arg-checks at compile-time:
0 <= _base < 63
class_names is not empty
class_names[0] is a string
I don't see where this is checked, did I miss something?
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Add a selftest script for dynamic-debug. The config requires
CONFIG_TEST_DYNAMIC_DEBUG=m and CONFIG_TEST_DYNAMIC_DEBUG_SUBMOD=m,
which tacitly requires either CONFIG_DYNAMIC_DEBUG=y or
CONFIG_DYNAMIC_DEBUG_CORE=y
ATM this has just basic_tests(), wh
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
DECLARE_DYNDBG_CLASSMAP() has a design error; its usage fails a basic
K&R rule: "define once, refer many times".
When DRM_USE_DYNAMIC_DEBUG=y, it is used across DRM core & drivers;
each invocation allocates/inits the classmap understood by that
modu
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Time for some thorough CI.
Also, the previous 18 patches could perhaps be replaced by a single
invocation of DYNDBG_CLASSMAP_USE, from a C-file linked into all drm
drivers & helpers. I didn't find such a file, nor a drm-client
linkage item in the M
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
The body of ddebug_attach_module_classes() is dominated by a
code-block that finds the contiguous subrange of classmaps matching on
modname, and saves it into the ddebug_table's info record.
Implement this block in a macro to accommodate different c
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
recompose struct _ddebug_info, inserting proper sub-structs.
The struct currently has 2 pairs of fields: descs, num_descs and
classes, num_classes. Several for-loops operate on these field pairs,
soon many more will be added.
Looping over these bl
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
Classmaps are stored in an elf section/array, but currently are
individually list-linked onto dyndbg's per-module ddebug_table for
operation. This is unnecessary.
Just like dyndbg's descriptors, classes are packed in compile order;
so even with many
Hi Jim,
Thanks a lot for this v3!
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
commit 1d926e259d8f ("vmlinux.lds.h: add HEADERED_SECTION_* macros")
I flubbed the defn of the outer 2 macros; they missed the extra arg
needed: _front/_hdr. Fix it now, before anyone notices.
I don't see any usag
Le 02/04/2025 à 19:41, Jim Cromie a écrit :
commit 47ea6f99d06e ("dyndbg: use ESCAPE_SPACE for cat control")
changed the control-file to display format strings with "\n" rather
than "\012". Update the docs to match the new reality.
Hi,
I don't know what is the process for dyndbg and how mu
On 2025-04-11 22:08, Melissa Wen wrote:
> Since [1], we can use drm_edid_product_id to get debug info from
> drm_edid instead of directly parsing EDID.
>
> Link:
> https://lore.kernel.org/dri-devel/cover.1712655867.git.jani.nik...@intel.com/
> [1]
> Signed-off-by: Melissa Wen
> ---
> .../amd/d
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Kamal, Asad
Sent: Tuesday, April 15, 2025 11:49
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo
Cc: Zhang, Hawking ; Ma, Le ; Zhang,
Morris ; Kamal,
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