On 2/20/2025 11:44 AM, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: Lazar, Lijo
>> Sent: Wednesday, February 19, 2025 10:18 PM
>> To: Kim, Jonathan ; Alex Deucher
>>
>> Cc: Deucher, Alexander ; Zhang, Jesse(Jie)
>> ; amd-gfx@lists.freedesktop.org; Kuehling, Felix
>
Avoid updating the vmid to 0 during the queue update process, as this may
trigger a wptr poll address page fault when a ring doorbell is activated
in doorbell_mode=1.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 4 ++--
1 file changed, 2 insertions(+), 2 delet
Use amdgpu_sriov_multi_vf_mode to replace amdgpu_sriov_vf(adev) &&
!amdgpu_sriov_is_pp_one_vf(adev).
Signed-off-by: Emily Deng
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 2 ++
drivers/gpu/drm/amd/pm/amdgpu_pm.c
In sriov multiple vf, Set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_MODE to 1 to read
WPTR from MQD.
Signed-off-by: Emily Deng
Acked-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 27 ---
2 files changed, 25 i
add nps info into eeprom records, and refine adding bad page
logic based on nps info.
Signed-off-by: ganglxie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 244 +-
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 25 +-
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h| 20 +-
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Wednesday, February 19, 2025 10:18 PM
> To: Kim, Jonathan ; Alex Deucher
>
> Cc: Deucher, Alexander ; Zhang, Jesse(Jie)
> ; amd-gfx@lists.freedesktop.org; Kuehling, Felix
> ; Zhu, Jiadong
> Subject: Re: [PATCH V7 3/9] drm/amdgpu:
On 2/19/2025 2:35 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> - Modify the VM invalidation engine allocation logic to handle SDMA page
> rings.
> SDMA page rings now share the VM invalidation engine with SDMA gfx rings
> instead of
> allocating a separate engine. Thi
On 2/20/2025 10:25 AM, Felix Kuehling wrote:
On 2025-02-18 15:51, Philip Yang wrote:
On 2025-02-18 11:01, Srinivasan Shanmugam wrote:
This commit addresses a circular locking dependency in the
svm_range_cpu_invalidate_pagetables function. The function previously
held a lock while determining
On 2025-02-18 15:51, Philip Yang wrote:
>
> On 2025-02-18 11:01, Srinivasan Shanmugam wrote:
>> This commit addresses a circular locking dependency in the
>> svm_range_cpu_invalidate_pagetables function. The function previously
>> held a lock while determining whether to perform an unmap or evictio
Signed-off-by: ganglxie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 239 +-
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 25 +-
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h| 20 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 7 +
4 files changed, 148 insertion
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Gao, Likun
Sent: Thursday, February 20, 2025 10:22
To: amd-gfx list
Cc: Deucher, Alexander ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: correct the name of m
On 2/20/2025 6:57 AM, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: Alex Deucher
>> Sent: Wednesday, February 19, 2025 6:09 PM
>> To: Kim, Jonathan
>> Cc: Deucher, Alexander ; Lazar, Lijo
>> ; Zhang, Jesse(Jie) ; amd-
>> g...@lists.freedesktop.org; Kuehling, Felix ;
On 2/19/2025 9:58 PM, Alex Deucher wrote:
> There was a quirk added to add a workaround for a Sapphire
> RX 5600 XT Pulse that didn't allow BAR resizing. However,
> the quirk caused a regression with runtim pm on Dell laptops
> using those chips, rather than narrowing the scope of the
> resizin
[AMD Official Use Only - AMD Internal Distribution Only]
From: Likun Gao
Correct the structure name admgpu_mes_pipe to amdgpu_mes_pipe.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 14 +++---
drivers/gpu/drm/
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, February 19, 2025 6:09 PM
> To: Kim, Jonathan
> Cc: Deucher, Alexander ; Lazar, Lijo
> ; Zhang, Jesse(Jie) ; amd-
> g...@lists.freedesktop.org; Kuehling, Felix ; Zhu,
> Jiadong
>
> Subject: Re: [PATCH V7 3/9] drm/amd
[Public]
> -Original Message-
> From: jesse.zh...@amd.com
> Sent: Thursday, February 13, 2025 12:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kuehling, Felix
> ; Kim, Jonathan ; Zhu,
> Jiadong ; Zhang, Jesse(Jie) ;
> Deucher, Alexander ; Zhang, Jesse(Jie)
>
> Subj
On Wed, Feb 19, 2025 at 3:29 PM Kim, Jonathan wrote:
>
> [Public]
>
> > -Original Message-
> > From: Deucher, Alexander
> > Sent: Wednesday, February 19, 2025 12:39 PM
> > To: Kim, Jonathan ; Lazar, Lijo ;
> > Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
> > Cc: Kuehling, Felix ; Zhu
On 2025-02-18 15:27, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: amd-gfx On Behalf Of Harish
>> Kasiviswanathan
>> Sent: Wednesday, February 12, 2025 5:04 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Kasiviswanathan, Harish
>> Subject: [PATCH 2/4] drm/amdkfd: Us
[Public]
> -Original Message-
> From: Deucher, Alexander
> Sent: Wednesday, February 19, 2025 12:39 PM
> To: Kim, Jonathan ; Lazar, Lijo ;
> Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix ; Zhu, Jiadong
>
> Subject: RE: [PATCH V7 3/9] drm/amdgpu: Add common lock
On 2025-02-19 13:46, Rodrigo Siqueira wrote:
> Signed-off-by: Rodrigo Siqueira
Reviewed-by: Harry Wentland
Harry
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c8b35ca294a0..a94abf72e117 100644
> --- a/MAINTAINER
On 2025-02-19 13:46, Rodrigo Siqueira wrote:
> Map all of my previously used email addresses to my @igalia.com address.
>
> Signed-off-by: Rodrigo Siqueira
Acked-by: Harry Wentland
Harry
> ---
> .mailmap | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/.mailmap b/.mailmap
> index
On Wed, Feb 19, 2025 at 3:00 PM Dr. David Alan Gilbert wrote:
>
> * Alex Deucher (alexdeuc...@gmail.com) wrote:
> > On Wed, Feb 19, 2025 at 2:04 PM Dr. David Alan Gilbert
> > wrote:
> > >
> > > Hi All,
> > > I think you may be misisng some wiring of nbif_v6_3_1_sriov_funcs.
> > >
> > > My scr
On Sun, Jan 26, 2025 at 3:38 AM Prike Liang wrote:
>
> Implement the GFX11 compute pipe reset. As the GFX11 CPFW
> still hasn't fully supported pipe reset yet, therefore
> disable the KCQ pipe reset temporarily.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 139
On Sun, Jan 26, 2025 at 3:38 AM Prike Liang wrote:
>
> Implement the kernel graphics queue pipe reset,and the driver
> will fallback to pipe reset when the queue reset fails. However,
> the ME FW hasn't fully supported pipe reset yet so disable the
> KGQ pipe reset temporarily.
>
> Signed-off-by:
On Wed, Feb 19, 2025 at 2:04 PM Dr. David Alan Gilbert
wrote:
>
> Hi All,
> I think you may be misisng some wiring of nbif_v6_3_1_sriov_funcs.
>
> My scripts noticed 'nbif_v6_3_1_sriov_funcs' was unused;
> It was added in:
> Commit: 894c6d3522d1 ("drm/amdgpu: Add nbif v6_3_1 ip block support
On Wed, Feb 19, 2025 at 1:55 PM Rodrigo Siqueira wrote:
>
> Users can check the file "/sys/kernel/debug/dri/0/amdgpu_firmware_info"
> to get information on the firmware loaded in the system. This file has
> multiple acronyms that are not documented in the glossary. This commit
> introduces some mi
Signed-off-by: Rodrigo Siqueira
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c8b35ca294a0..a94abf72e117 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1024,7 +1024,7 @@ F:drivers/crypto/ccp/hsti.*
AMD DISPLAY CORE
M:
Users can check the file "/sys/kernel/debug/dri/0/amdgpu_firmware_info"
to get information on the firmware loaded in the system. This file has
multiple acronyms that are not documented in the glossary. This commit
introduces some missing acronyms to the AMD glossary documentation. The
meaning of ea
On Wed, Feb 19, 2025 at 1:15 PM Sunil Khatri wrote:
>
> Update the *handle to amdgpu_ip_block ptr for all
> functions pointers of is_idle.
>
> Signed-off-by: Sunil Khatri
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/a
Map all of my previously used email addresses to my @igalia.com address.
Signed-off-by: Rodrigo Siqueira
---
.mailmap | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.mailmap b/.mailmap
index 5e829da09e7f..64413bbc286c 100644
--- a/.mailmap
+++ b/.mailmap
@@ -583,6 +583,8 @@ Richard Leitne
This patchset changes my status from a Maintainer of the display code to
a reviewer, and it also adds an entry to my name in the mailmap file.
Thanks
Siqueira
Rodrigo Siqueira (2):
MAINTAINERS: Change my role from Maintainer to Reviewer
mailmap: Add entry for Rodrigo Siqueira
.mailmap|
Update the *handle to amdgpu_ip_block ptr for all
functions pointers of is_idle.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
drivers/g
[Public]
Patches 1-2 and 4-9 are:
Reviewed-by: Alex Deucher
For patch 3, I don't have a strong preference.
Alex
> -Original Message-
> From: jesse.zh...@amd.com
> Sent: Thursday, February 13, 2025 12:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kuehling, Feli
[Public]
> -Original Message-
> From: Kim, Jonathan
> Sent: Tuesday, February 18, 2025 12:42 PM
> To: Lazar, Lijo ; Zhang, Jesse(Jie)
> ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kuehling, Felix
> ; Zhu, Jiadong
> Subject: RE: [PATCH V7 3/9] drm/amdgpu: Add common lock an
On Wed, Feb 19, 2025 at 11:39 AM Alex Deucher wrote:
>
> There was a quirk added to add a workaround for a Sapphire
> RX 5600 XT Pulse that didn't allow BAR resizing. However,
> the quirk caused a regression with runtim pm on Dell laptops
runtim -> runtime fixed locally.
Alex
> using those chi
[Public]
Should we just check the amdgpu runpm param value?
Thanks,
Lijo
From: Alex Deucher
Sent: Wednesday, February 19, 2025 9:45:28 PM
To: Lazar, Lijo
Cc: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: disable BAR resize
On 2/18/2025 17:13, David Yat Sin wrote:
@@ -107,6 +107,7 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
+ m->cp_hqd_pq_c
There was a quirk added to add a workaround for a Sapphire
RX 5600 XT Pulse that didn't allow BAR resizing. However,
the quirk caused a regression with runtim pm on Dell laptops
using those chips, rather than narrowing the scope of the
resizing quirk, add a quirk to prevent amdgpu from resizing
th
On Wed, Feb 19, 2025 at 10:42 AM Lazar, Lijo wrote:
>
>
>
> On 2/19/2025 8:02 PM, Alex Deucher wrote:
> > On Tue, Feb 18, 2025 at 11:05 AM Lazar, Lijo wrote:
> >>
> >>
> >>
> >> On 2/18/2025 8:38 PM, Alex Deucher wrote:
> >>> There was a quirk added to add a workaround for a Sapphire
> >>> RX 560
On Wed, Feb 19, 2025 at 10:53 AM Sunil Khatri wrote:
>
> Update the *handle to amdgpu_ip_block ptr for all
> functions pointers of get_clockgating_state.
>
> Signed-off-by: Sunil Khatri
Thanks,
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
> drivers/gp
Update the *handle to amdgpu_ip_block ptr for all
functions pointers of get_clockgating_state.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
drivers/gpu
On 2/19/2025 8:02 PM, Alex Deucher wrote:
> On Tue, Feb 18, 2025 at 11:05 AM Lazar, Lijo wrote:
>>
>>
>>
>> On 2/18/2025 8:38 PM, Alex Deucher wrote:
>>> There was a quirk added to add a workaround for a Sapphire
>>> RX 5600 XT Pulse that didn't allow BAR resizing. However,
>>> the quirk casus
On Tue, Feb 18, 2025 at 11:05 AM Lazar, Lijo wrote:
>
>
>
> On 2/18/2025 8:38 PM, Alex Deucher wrote:
> > There was a quirk added to add a workaround for a Sapphire
> > RX 5600 XT Pulse that didn't allow BAR resizing. However,
> > the quirk casused a regression on Dell laptops using those
> > chi
On Wed, Feb 19, 2025 at 1:46 AM Josh Poimboeuf wrote:
>
> On Mon, Feb 17, 2025 at 11:13:43AM +0800, Huacai Chen wrote:
> > On Thu, Feb 13, 2025 at 10:51 AM Josh Poimboeuf wrote:
> > >
> > > On Wed, Feb 12, 2025 at 03:22:45PM +0800, Huacai Chen wrote:
> > > > > The new series now has 7 patches:
>
Am 19.02.25 um 07:20 schrieb jesse.zh...@amd.com:
> From: "jesse.zh...@amd.com"
>
> - Modify the VM invalidation engine allocation logic to handle SDMA page
> rings.
> SDMA page rings now share the VM invalidation engine with SDMA gfx rings
> instead of
> allocating a separate engine. This c
On Tue, 2025-02-18 at 14:17 -0800, Matthew Brost wrote:
> On Tue, Feb 18, 2025 at 06:26:15PM +, Tvrtko Ursulin wrote:
> >
> > On 18/02/2025 12:26, Philipp Stanner wrote:
> > > Thx for the updated version. Overlooked it, I was out on Friday.
> > > See
> > > below
> > >
> > > On Fri, 2025-02-14
Op 14-02-2025 om 09:07 schreef Xiang Liu:
From: Hawking Zhang
Encode the error information in CPER format and commit
to the cper ring
Signed-off-by: Hawking Zhang
Reviewed-by: Yang Wang
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 32 +
1 fi
On 18/02/2025 12:26, Philipp Stanner wrote:
Thx for the updated version. Overlooked it, I was out on Friday. See
below
On Fri, 2025-02-14 at 10:19 +, Tvrtko Ursulin wrote:
Idea is to add helpers for peeking and popping jobs from entities
with
the goal of decoupling the hidden assumption i
From: "jesse.zh...@amd.com"
- Modify the VM invalidation engine allocation logic to handle SDMA page rings.
SDMA page rings now share the VM invalidation engine with SDMA gfx rings
instead of
allocating a separate engine. This change ensures efficient resource
management and
avoids the is
From: "jesse.zh...@amd.com"
Increase the maximum number of rings supported by the AMDGPU driver from 132 to
148.
This change is necessary to enable support for the SDMA page ring.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
1 file changed, 1 insertion(+), 1
On 2/19/2025 1:30 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> - Modify the VM invalidation engine allocation logic to handle SDMA page
> rings.
> SDMA page rings now share the VM invalidation engine with SDMA gfx rings
> instead of
> allocating a separate engine. Thi
From: "jesse.zh...@amd.com"
- Modify the VM invalidation engine allocation logic to handle SDMA page rings.
SDMA page rings now share the VM invalidation engine with SDMA gfx rings
instead of
allocating a separate engine. This change ensures efficient resource
management and
avoids the is
From: "jesse.zh...@amd.com"
Increase the maximum number of rings supported by the AMDGPU driver from 132 to
148.
This change is necessary to enable support for the SDMA page ring.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
1 file changed, 1 insertion(+), 1
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