Since pmfw supports for smuv13_0_6 is limited to 8 jpeg rings per instance,
which is the max for jpeg_v_4_0_3. Limit it to same to avoid out
of bound access.
Fixes: c80feef27112 ("drm/amd/pm: Limit to 8 jpeg rings per instance")
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Lazar, Lijo
Sent: Friday, February 14, 2025 2:54 PM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kim, Jonathan
; Zhu, Jiadong ; Prosyak, Vitaly
Subject: Re: [PATCH 2/2] d
On 2/14/2025 12:14 PM, Zhang, Jesse(Jie) wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Lijo,
> -Original Message-
> From: Lazar, Lijo
> Sent: Friday, February 14, 2025 2:10 PM
> To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ;
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Lijo,
-Original Message-
From: Lazar, Lijo
Sent: Friday, February 14, 2025 2:10 PM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kim, Jonathan
; Zhu, Jiadong ; Prosyak, Vitaly
Subject: Re: [PAT
On 2/14/2025 11:25 AM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This patch updates the SDMA v4.4.2 software initialization to enable per-queue
> reset support when the MEC firmware version is 0xb0 or higher and the PMFW
> supports SDMA reset.
>
> The following changes are
On 2/13/2025 9:20 PM, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: Lazar, Lijo
>> Sent: Thursday, February 13, 2025 1:35 AM
>> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH] drm/amdgpu: simplify xgmi peer info calls
>>
>>
>>
>> On 2/12/202
From: "jesse.zh...@amd.com"
This patch updates the SDMA v4.4.2 software initialization to enable per-queue
reset support when the MEC firmware version is 0xb0 or higher and the PMFW
supports SDMA reset.
The following changes are included:
- Added a condition to check if the MEC firmware version
From: "jesse.zh...@amd.com"
This patch introduces a new function to check if the SMU supports resetting the
SDMA engine.
This capability check ensures that the driver does not attempt to reset the
SDMA engine
on hardware that does not support it.
The following changes are included:
- New funct
SRIOV VF does not have write access to AGP BAR regs.
Skip the writes to avoid a dmesg warning.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
b/drivers/
Aldebaran SRIOV VF does not have write permissions to GRBM_CTNL.
This access can be skipped to avoid a dmesg warning.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b
Aldebaran SRIOV VF cannot access the power brake feature regs.
The accesses can be skipped to avoid a dmesg warning.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/d
On Mon, 27 Jan 2025 16:59:38 -0300, André Almeida wrote:
> The goal of this work is to find a nice way to allow amdgpu to perform
> async page flips in the overlay plane as well, not only on the primary
> one. Currently, when using the atomic uAPI, this is the only type of
> plane allowed to do asy
On Wed, Feb 12, 2025 at 01:36:58PM +0100, Philipp Stanner wrote:
> On Wed, 2025-02-12 at 12:30 +, Tvrtko Ursulin wrote:
> >
> > On 12/02/2025 10:40, Philipp Stanner wrote:
> > > On Wed, 2025-02-12 at 09:32 +, Tvrtko Ursulin wrote:
> > > >
> > > > On 12/02/2025 09:02, Philipp Stanner wrote
On Thu, Feb 13, 2025 at 1:32 PM Srinivasan Shanmugam
wrote:
>
> Change the function name from vcn_v2_5_enable_clock_gating_inst
> to vcn_v2_5_enable_clock_gating to ensure consistency in naming.
>
> Fixes the below with gcc W=1:
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:781: warning: expecting proto
On 2/14/2025 12:09 AM, Alex Deucher wrote:
This should not be called on chips without MES so check if
MES is enabled and if the cleaner shader is supported.
Fixes: 8521e3c5f058 ("drm/amd/amdgpu: limit single process inside MES")
Signed-off-by: Alex Deucher
Cc: Shaoyun Liu
Cc: Srinivasan Shanmug
This should not be called on chips without MES so check if
MES is enabled and if the cleaner shader is supported.
Fixes: 8521e3c5f058 ("drm/amd/amdgpu: limit single process inside MES")
Signed-off-by: Alex Deucher
Cc: Shaoyun Liu
Cc: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_g
On 2024-12-19 23:33, Alex Hung wrote:
This adds support for a 3D LUT.
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. Multiplier
3. 3x4 CTM
4. 1D curve colorop
5. 1D LUT
6. 3D LUT
7. 1D curve colorop
8. 1D LUT
Signed-off-by: Alex Hung
---
v7:
- Simplify
On Thu, Feb 13, 2025 at 12:57 PM Srinivasan Shanmugam
wrote:
>
> By adding these NULL pointer checks and improving error handling, we can
> prevent crashes when the enforce_isolation sysfs file is accessed on
> non-supported systems.
Can you clarify what the issue is? The code seems correct as i
Change the function name from vcn_v2_5_enable_clock_gating_inst
to vcn_v2_5_enable_clock_gating to ensure consistency in naming.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:781: warning: expecting prototype for
vcn_v2_5_enable_clock_gating_inst(). Prototype was for
vcn_v2
By adding these NULL pointer checks and improving error handling, we can
prevent crashes when the enforce_isolation sysfs file is accessed on
non-supported systems.
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 17 +++
On Thu, Feb 13, 2025 at 12:03 PM Nikita Zhandarovich
wrote:
>
> Gentle ping :)
Was already applied:
https://gitlab.freedesktop.org/agd5f/linux/-/commit/189abca05a89fc7b422811e497a7116b3e4f4dca
Thanks,
Alex
>
> On 1/14/25 16:58, Nikita Zhandarovich wrote:
> > This patch removes useless NULL poi
On 2024-12-19 23:33, Alex Hung wrote:
This adds support for a 3x4 color transformation matrix.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-ctm_3x4_50_desat
kms_colorop --run plane-XR30-XR30-ctm_3x4_overdrive
kms_colorop --run plane-XR30-XR30-ctm_3x4_oversa
On 2024-12-19 23:33, Alex Hung wrote:
This patch adds colorops for custom 1D LUTs in the SHAPER and
BLND HW blocks.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut-srgb_eotf_lut
The color p
On 2024-12-19 23:33, Alex Hung wrote:
From: Harry Wentland
This adds support for the BT.709/BT.2020 transfer functions
on all current 1D curve plane colorops, i.e., on DEGAM, SHAPER,
and BLND blocks.
With this change the following IGT subtests pass:
kms_colorop --run plane-XR30-XR30-bt2020_
On 2024-12-19 23:33, Alex Hung wrote:
Expose one 1D curve colorop with support for
DRM_COLOROP_1D_CURVE_SRGB_EOTF and program HW to perform
the sRGB transform when the colorop is not in bypass.
With this change the following IGT test passes:
kms_colorop --run plane-XR30-XR30-srgb_eotf
The co
On Wed, Feb 12, 2025 at 01:25:05PM -0500, Rodrigo Vivi wrote:
> On Wed, Feb 12, 2025 at 08:57:10AM +0200, Raag Jadav wrote:
> > On Tue, Feb 04, 2025 at 12:35:23PM +0530, Raag Jadav wrote:
> > > This series introduces device wedged event in DRM subsystem and uses it
> > > in xe, i915 and amdgpu driv
We advertise DCC as supported for NV12/P010 formats on GFX12,
but it would fail on this check on commit.
Signed-off-by: David Rosca
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/a
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, February 13, 2025 1:35 AM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: simplify xgmi peer info calls
>
>
>
> On 2/12/2025 9:27 PM, Jonathan Kim wrote:
> > Deprecate KFD XGMI peer
On 2025-02-12 23:33, Deng, Emily wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
*From:*Yang, Philip
*Sent:* Wednesday, February 12, 2025 10:31 PM
*To:* Deng, Emily ; Yang, Philip
; Chen, Xiaogang ;
amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amdkfd: Fix the de
Hi Dave, Simona,
Fixes for 6.14.
The following changes since commit f245b400a223a71d6d5f4c72a2cb9b573a7fc2b6:
Revert "drm/amd/display: Use HW lock mgr for PSR1" (2025-02-04 17:47:34 -0500)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-
Hi,
Changes looks good to me.
Series is Reviewed-by: Saleemkhan Jamadar
Regards,
Saleem
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, February 13, 2025 3:18 AM
To: amd-gfx@lists.freedesktop.org
C
Hello Philip,
Philip Yang writes:
On 2025-02-12 17:42, Uwe Kleine-König wrote:
#regzbot introduced: 68e599db7a549f010a329515f3508d8a8c3467a4
#regzbot monitor: https://bugs.debian.org/1093124
Hello,
On Thu, Jul 18, 2024 at 05:05:53PM -0400, Philip Yang wrote:
Find user queue rptr, ring
If firmware supported NPS modes are available through CAP register, use
those values for supported NPS modes.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 36 +++
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/
On 2/13/2025 1:10 AM, Amber Lin wrote:
> As far as the number of XCCs, the number of compute partitions, and the
> number of memory partitions qualify, CPX is valid.
>
> Change-Id: I65696f25e2afd75f2f4a177dabc0991b15293d9a
> Signed-off-by: Amber Lin
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> -
#regzbot introduced: 68e599db7a549f010a329515f3508d8a8c3467a4
#regzbot monitor: https://bugs.debian.org/1093124
Hello,
On Thu, Jul 18, 2024 at 05:05:53PM -0400, Philip Yang wrote:
> Find user queue rptr, ring buf, eop buffer and cwsr area BOs, and
> check BOs are mapped on the GPU with correct si
Remove the repeated word "the" in docs.
Signed-off-by: Charles Han
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst
b/Documentation/gpu/amdgpu/display/dc-debug.rst
index 013f63b271
On Wed, Feb 12, 2025 at 06:02:15PM -0500, Philip Yang wrote:
> [html-content]
Are you aware that your mail is hard for some people (e.g. those like me
who read their mail in a terminal, but also consider people who have to
rely on braille readers) to read and also isn't properly archived on
lore.k
On 2/13/2025 2:45 PM, Sundararaju, Sathishkumar wrote:
>
>
> On 2/13/2025 1:35 PM, Lazar, Lijo wrote:
>>
>> On 2/13/2025 1:07 PM, Sundararaju, Sathishkumar wrote:
>>> On 2/13/2025 12:16 PM, Lazar, Lijo wrote:
On 2/13/2025 8:24 AM, Sathishkumar S wrote:
> Add helper functions to handle
On 2/13/2025 1:35 PM, Lazar, Lijo wrote:
On 2/13/2025 1:07 PM, Sundararaju, Sathishkumar wrote:
On 2/13/2025 12:16 PM, Lazar, Lijo wrote:
On 2/13/2025 8:24 AM, Sathishkumar S wrote:
Add helper functions to handle per-instance and per-core
initialization and deinitialization in JPEG4_0_3.
On 2/13/2025 1:07 PM, Sundararaju, Sathishkumar wrote:
>
> On 2/13/2025 12:16 PM, Lazar, Lijo wrote:
>>
>> On 2/13/2025 8:24 AM, Sathishkumar S wrote:
>>> Add helper functions to handle per-instance and per-core
>>> initialization and deinitialization in JPEG4_0_3.
>>>
>>> Signed-off-by: Sathis
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