[Public]
Reviewed-by: Yifan Zhang
-Original Message-
From: Huang, Tim
Sent: Saturday, February 8, 2025 11:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amdgpu: add discovery support for DCN IP version 3.6.0
Add discov
From: "jesse.zh...@amd.com"
This commit introduces several improvements to the SDMA reset logic:
1. Added `cached_rptr` to the `amdgpu_ring` structure to store the read pointer
before a reset, ensuring proper state restoration after reset.
2. Introduced `gfx_guilty` and `page_guilty` flags i
From: "jesse.zh...@amd.com"
This commit introduces a caller parameter to the amdgpu_sdma_reset_instance
function to differentiate
between reset requests originating from the KGD and KFD.
This change ensures proper synchronization between KGD and KFD during SDMA
resets.
If the caller is KFD, th
From: "jesse.zh...@amd.com"
This patch refactors the SDMA reset functionality in the `sdma_v4_4_2` driver
to improve modularity and support shared usage between AMDGPU and KFD. The
changes include:
1. **Refactored SDMA Reset Logic**:
- Split the `sdma_v4_4_2_reset_queue` function into two sep
From: "jesse.zh...@amd.com"
This patch introduces shared SDMA reset functionality between AMDGPU and KFD.
The implementation includes the following key changes:
1. Added `amdgpu_sdma_reset_queue`:
- Resets a specific SDMA queue by instance ID.
- Invokes registered pre-reset and post-reset
Add discovery entry for DCN IP version 3.6.0.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index eca431e52038..998a5e48
[AMD Official Use Only - AMD Internal Distribution Only]
Ping...
Emily Deng
Best Wishes
>-Original Message-
>From: Emily Deng
>Sent: Friday, February 7, 2025 6:28 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH] drm/amdkfd: Fix the deadlock in svm_range_re
VALU instructions with SGPR source need wait states to avoid hazard
with SALU using different SGPR.
v2: Eliminate some hazards to reduce code explosion
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 677 ++
.../amd/amdkfd/cwsr_t
From: Luan Arcanjo
All dce command_table_helper's shares a copy-pasted collection
of copy-pasted functions, which are: phy_id_to_atom,
clock_source_id_to_atom_phy_clk_src_id, and engine_bp_to_atom.
This patch removes the multiple copy-pasted by creating a
common command table and make the comman
From: Luan Arcanjo
All dce command_table_helper's shares a copy-pasted collection
of copy-pasted functions, which are: phy_id_to_atom,
clock_source_id_to_atom_phy_clk_src_id, and engine_bp_to_atom.
This patch removes the multiple copy-pasted by creating a
common command table and make the comman
[Public]
I think part of the problem is that gmc.xgmi.supported has weird usage and
definition.
It's partly says that it has potential to be supported by IP version, but
doesn't actually say anything about real support but assumed say it has real
support in amdgpu_xgmi.c usage.
Real support is
This initializes drm/amd/amdgpu version 11.5.2
Signed-off-by: YING LI
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 +
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
drivers/
This initializes drm/amd/pm version 11.5.2
Signed-off-by: YING LI
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +++
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 12
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu
Added the fixes tag and applied. Thanks!
On Fri, Feb 7, 2025 at 6:07 AM Lazar, Lijo wrote:
>
>
>
> On 2/7/2025 11:58 AM, Jiang Liu wrote:
> > In function psp_init_cap_microcode(), it should bail out when failed to
> > load firmware, otherwise it may cause invalid memory access.
> >
> > Signed-of
Applied. Thanks!
On Fri, Feb 7, 2025 at 6:17 AM Lazar, Lijo wrote:
>
>
>
> On 2/7/2025 11:58 AM, Jiang Liu wrote:
> > Reset psp->cmd to NULL after releasing the buffer in function psp_sw_fini().
> >
> > Signed-off-by: Jiang Liu
>
> Reviewed-by: Lijo Lazar
>
> Thanks,
> Lijo
>
> > ---
>
Applied. Thanks!
On Fri, Feb 7, 2025 at 3:02 AM Lazar, Lijo wrote:
>
>
>
> On 2/7/2025 12:14 PM, Jiang Liu wrote:
> > It malicious user provides a small pptable through sysfs and then
> > a bigger pptable, it may cause buffer overflow attack in function
> > smu_sys_set_pp_table().
> >
> > Signed
[Public]
Another try.. if it helps (you or someone else)
This series introduces two functions for maintenance.
amdgpu_xgmi_init_info - This is to initialize any XGM related static
information. Now it's called as soon as XGMI version is discovered. Now, if
that is causing some confusion, then I
On 2025-02-06 16:07, Harish
Kasiviswanathan wrote:
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.
v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
Modi
[Public]
Well ... I don't know what other feedback I can give here then.
We're bouncing back and forth talking about language/function/logical structure
or whatever.
I'm of the opinion that there are too many unnecessary wrappers here and am
biased to unbroken steps that make it easier to debug/
In some ASICs L2 cache info may miss in kfd topology,
because the first bitmap may be empty, that means
the first cu may be inactive, so to find the first
active cu will solve the issue.
v2: Only find the first active cu in the first xcc
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/
[Public]
It so happens that driver gets part of the XGMI information through registers
in GMC. The intent of those registers is to help GMC to figure out memory
access when device part of XGMI hive. Driver using those regs doesn't mean XGMI
is like a sub ip of GMC, it remains separate.
Thanks,
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Friday, February 7, 2025 10:18 AM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking
> Subject: Re: [PATCH 3/4] drm/amdgpu: Initialize xgmi info during discovery
>
>
>
> On 2/7/2025 8:06 PM, Kim, Jonathan wro
Replace a copy of DRM scheduler's to_drm_sched_job with a copy of a newly
added __drm_sched_entity_queue_pop.
This allows breaking the hidden dependency that queue_node has to be the
first element in struct drm_sched_job.
A comment is also added with a reference to the mailing list discussion
exp
We can re-order some struct members and take u32 credits outside of the
pointer sandwich and also for the last_dependency member we can get away
with an unsigned int since for dependency we use xa_limit_32b.
Pahole report before:
/* size: 160, cachelines: 3, members: 14 */
/* sum m
Lets add some helpers for peeking and popping from the job queue which allows us
to re-order the fields in struct drm_sched_job and remove one hole.
v2:
* Add header file for internal scheduler API.
* Add helper for peeking too. (Danilo)
* Add (temporary?) drm_sched_cancel_all_jobs() helper to
On 06/02/2025 16:54, Danilo Krummrich wrote:
On Thu, Feb 06, 2025 at 04:40:29PM +, Tvrtko Ursulin wrote:
Idea is to add helpers for peeking and popping jobs from entities with
the goal of decoupling the hidden assumption in the code that queue_node
is the first element in struct drm_sched_
Replace a copy of DRM scheduler's to_drm_sched_job with a copy of a newly
added __drm_sched_entity_queue_pop.
This allows breaking the hidden dependency that queue_node has to be the
first element in struct drm_sched_job.
A comment is also added with a reference to the mailing list discussion
exp
Now that we have a header file for internal scheduler interfaces we can
move some more prototypes into it. By doing that we eliminate the chance
of drivers trying to use something which was not intended to be used.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matth
[AMD Official Use Only - AMD Internal Distribution Only]
I'm not sure why there is no mes.resource_1_gpu_addr for mes v12 , probably
sriov team still not support it . But we do need this cleaner_fence_gpu_addr
for both mes v11 and v12 . What MES need is a GPU addr it can update a 32 bit
valu
Do a bit of house keeping in gpu_scheduler.h by grouping the API by type
of object it operates on.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
include/drm/gpu_scheduler.h | 60 -
1 file c
On 2025-02-06 22:41, Lazar, Lijo wrote:
On 2/6/2025 10:18 PM, Eric Huang wrote:
I understand your concern. KFD currently only reports one L2 instance,
but not every L2 instance. If customers want to have more detail in all
available L2 info, we probably can change the logic in this function,
Lets add some helpers for peeking and popping from the job queue which allows us
to re-order the fields in struct drm_sched_job and remove one hole.
As in the process we have added a header file for scheduler internal prototypes,
lets also use it more and cleanup the "exported" header a bit.
v2:
On 06/02/2025 16:58, Danilo Krummrich wrote:
On 2/6/25 5:40 PM, Tvrtko Ursulin wrote:
Lets add some helpers for peeking and popping from the job queue which
allows us
to re-order the fields in struct drm_sched_job and remove one hole.
I think you forgot to add the dri-devel list.
Can't fet
Idea is to add helpers for peeking and popping jobs from entities with
the goal of decoupling the hidden assumption in the code that queue_node
is the first element in struct drm_sched_job.
That assumption usually comes in the form of:
while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_
Helper is for scheduler internal use so lets hide it from DRM drivers
completely.
At the same time we change the method of checking whethere there is
anything in the queue from peeking to looking at the node count.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matt
We can re-order some struct members and take u32 credits outside of the
pointer sandwich and also for the last_dependency member we can get away
with an unsigned int since for dependency we use xa_limit_32b.
Pahole report before:
/* size: 160, cachelines: 3, members: 14 */
/* sum m
Idea is to add helpers for peeking and popping jobs from entities with
the goal of decoupling the hidden assumption in the code that queue_node
is the first element in struct drm_sched_job.
That assumption usually comes in the form of:
while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_
On 2/7/2025 8:06 PM, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: Lazar, Lijo
>> Sent: Friday, February 7, 2025 9:20 AM
>> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Hawking
>> Subject: Re: [PATCH 3/4] drm/amdgpu: Initialize xgmi info during di
On 2/7/2025 7:50 PM, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: Lazar, Lijo
>> Sent: Thursday, February 6, 2025 10:51 PM
>> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Hawking
>> Subject: Re: [PATCH 2/4] drm/amdgpu: Add xgmi speed/width relate
Am 07.02.25 um 15:53 schrieb Philip Yang:
On 2025-02-07 05:17, Christian König wrote:
Am 30.01.25 um 17:19 schrieb Philip Yang:
On 2025-01-29 11:40, Christian König wrote:
Am 23.01.25 um 21:39 schrieb Philip Yang:
SVM migration unmap pages from GPU and then update mapping to GPU to
recover pa
On 2025-02-07 05:17, Christian König
wrote:
Am
30.01.25 um 17:19 schrieb Philip Yang:
On 2025-01-29 11:40, Christian König
wrote:
Am 23.01.25 um 21:39 schrieb Philip
Yang:
SVM migration unmap
Am 07.02.25 um 15:43 schrieb Alex Deucher:
From: Srinivasan Shanmugam
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the
From: Srinivasan Shanmugam
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are
It's GPU page size not CPU page size. In most cases they
are the same, but not always. This can lead to overallocation
on systems with larger pages.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Friday, February 7, 2025 9:20 AM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking
> Subject: Re: [PATCH 3/4] drm/amdgpu: Initialize xgmi info during discovery
>
>
>
> On 2/7/2025 7:29 PM, Kim, Jonathan wrot
On Fri, Feb 7, 2025 at 5:02 AM Srinivasan Shanmugam
wrote:
>
> This commit introduces enhancements to the handling of the cleaner
> shader fence in the AMDGPU MES driver:
>
> - The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
> KIQ (Kernel Interface Queue) to request the cle
On 2/7/2025 7:29 PM, Kim, Jonathan wrote:
> [Public]
>
>> -Original Message-
>> From: Lazar, Lijo
>> Sent: Thursday, February 6, 2025 10:56 PM
>> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Hawking
>> Subject: Re: [PATCH 3/4] drm/amdgpu: Initialize xgmi info during
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, February 6, 2025 10:51 PM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking
> Subject: Re: [PATCH 2/4] drm/amdgpu: Add xgmi speed/width related info
>
>
>
> On 2/7/2025 4:56 AM, Kim, Jonathan wrote
[AMD Official Use Only - AMD Internal Distribution Only]
This fence address will be used in MES after set_hw_resource_1 API, so you can
not free the mem directly in set_hw_resource_1 function .
You can simply free it inside mes hw_fini function to make it balance.
Another more preferred way
Am 07.02.25 um 11:09 schrieb Srinivasan Shanmugam:
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensu
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, February 6, 2025 10:56 PM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking
> Subject: Re: [PATCH 3/4] drm/amdgpu: Initialize xgmi info during discovery
>
>
>
> On 2/7/2025 5:03 AM, Kim, Jonathan w
On 07/02/2025 11:02, Philipp Stanner wrote:
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("drm/nouve
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("drm/nouveau: Improve variable name in
nouveau_sched_init(
On 2/7/2025 11:58 AM, Jiang Liu wrote:
> In function psp_init_cap_microcode(), it should bail out when failed to
> load firmware, otherwise it may cause invalid memory access.
>
> Signed-off-by: Jiang Liu
You may also add
Fixes: 07dbfc6b102e ("drm/amd: Use `amdgpu_ucode_*` helpers fo
On 2/7/2025 11:58 AM, Jiang Liu wrote:
> Enhance error handling in function psp_sw_init() by:
> 1) bail out when failed to allocate memory
> 2) release allocated resource on error
> 3) introduce helper function psp_bo_init()
>
> Signed-off-by: Jiang Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdg
On 2/7/2025 11:58 AM, Jiang Liu wrote:
> Reset psp->cmd to NULL after releasing the buffer in function psp_sw_fini().
>
> Signed-off-by: Jiang Liu
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 d
On 2/7/2025 12:14 PM, Jiang Liu wrote:
> Minor code style enhancement for smu.
>
> Signed-off-by: Jiang Liu
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 2 +-
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
It will hit deadlock in svm_range_restore_work ramdonly.
Detail as below:
1.svm_range_restore_work
->svm_range_list_lock_and_flush_work
->mmap_write_lock
2.svm_range_restore_work
->svm_range_validate_and_map
->amdgpu_vm_update_range
->amdgpu_vm_ptes_update
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are handled in a controlled manne
Am 30.01.25 um 17:19 schrieb Philip Yang:
On 2025-01-29 11:40, Christian König wrote:
Am 23.01.25 um 21:39 schrieb Philip Yang:
SVM migration unmap pages from GPU and then update mapping to GPU to
recover page fault. Currently unmap clears the PDE entry for range
length >= huge page and may fre
[AMD Official Use Only - AMD Internal Distribution Only]
typo:
amdgpu_device_wb_put() -> amdgpu_device_wb_free()
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Wang,
Yang(Kevin)
Sent: Friday, February 7, 2025 17:26
To: SHANMUGAM, SRINIVASAN ; Koenig, Christian
; Deuc
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are handled in a controlled manne
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: amd-gfx On Behalf Of Srinivasan
Shanmugam
Sent: Friday, February 7, 2025 17:16
To: Koenig, Christian ; Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
; cao, lin ; Chen, JingW
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are handled in a controlled manne
On 2/7/2025 11:33 AM, Emily Deng wrote:
> In sriov multiple vf, Set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_MODE to 1 to
> read WPTR from MQD.
>
> Signed-off-by: Emily Deng
Acked-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
> .../gpu/drm/
> 2025年2月7日 16:34，Lazar, Lijo 写道：
>
>
>
> On 2/7/2025 2:00 PM, Gerry Liu wrote:
>>
>>
>>> 2025年2月7日 16:04，Lazar, Lijo 写道：
>>>
>>>
>>>
>>> On 2/7/2025 12:14 PM, Jiang Liu wrote:
As pwfw resets entrycount when device is suspended, so we should
accmulate the gfx_off_entrycount v
On 2/7/2025 2:00 PM, Gerry Liu wrote:
>
>
>> 2025年2月7日 16:04，Lazar, Lijo 写道：
>>
>>
>>
>> On 2/7/2025 12:14 PM, Jiang Liu wrote:
>>> As pwfw resets entrycount when device is suspended, so we should
>>> accmulate the gfx_off_entrycount value instead of save the last value
>>> of it.
>>>
>>> Sig
> 2025年2月7日 16:04，Lazar, Lijo 写道：
>
>
>
> On 2/7/2025 12:14 PM, Jiang Liu wrote:
>> As pwfw resets entrycount when device is suspended, so we should
>> accmulate the gfx_off_entrycount value instead of save the last value
>> of it.
>>
>> Signed-off-by: Jiang Liu
>> ---
>> drivers/gpu/drm/a
On 2/7/2025 11:33 AM, Emily Deng wrote:
> Use amdgpu_sriov_multi_vf_mode to replace amdgpu_sriov_vf(adev) &&
> !amdgpu_sriov_is_pp_one_vf(adev).
>
> Signed-off-by: Emily Deng
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
> driver
On 2/7/2025 12:14 PM, Jiang Liu wrote:
> As pwfw resets entrycount when device is suspended, so we should
> accmulate the gfx_off_entrycount value instead of save the last value
> of it.
>
> Signed-off-by: Jiang Liu
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 +++---
> 1 file change
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