Hi
Am 18.01.25 um 03:37 schrieb Marek Olšák:
[...]
3) Implementing DRM_FORMAT_MOD_LINEAR as having 256B pitch and offset
alignment. This is what we do today. Even if Intel and some AMD chips
can do 64B or 128B alignment, they overalign to 256B. With so many
AMD+NV laptops out there, NV is p
GCC raises a parameter compatibility error log for the
amdgpu_vkms_early_init function because it previously accepted
a generic `void *handle` parameter. This change updates the
function signature to accept a specific `struct amdgpu_ip_block *`
parameter instead.
error log:
/tmp/amd.fwXY79Rm/amd/a
Reviewed-by: Simon Ser
change the config of cgcg on gfx12
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 2a7199880041..16842fa8dae0 100644
--- a
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks for the patches.
We currently have no plans to include RAS programming as part of the device
suspend/resume sequence. Instead, we are focusing on a series of clean up
patches and a new RAS software module that will eliminate all le
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Lazar, Lijo
Sent: Friday, January 17, 2025 23:14
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad ; Wang,
Yang(Kevin)
Subject: [PATCH] drm/amd/pm: Use correct macros
[Why]
Under SRIOV VF, driver send a VF unsupportted smu message causing
a failure.
[How]
Update smu_v13_0_0 message mapping table based on PMFW.
Signed-off-by: Yifan Zha
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
