On 11/19/2024 12:06 PM, Kenneth Feng wrote:
> disable pcie speed switching on Intel platform for smu v14.0.2/3
> based on Intel's requirement.
> v2: align the setting with smu v13.
>
> Signed-off-by: Kenneth Feng
Need to revisit later for keeping common logic at one place.
Reviewed-by: Lijo
All legacy RAS bad pages are generated in NPS1 mode, but new bad page can be
generated in any NPS mode, so we can't use retired_page stored on eeprom
directly in non-nps1 mode even for legacy data. We need to take different
actions for different data, new data can be identified from old data by
UMC
Take R13 and column bits as a whole for UMC v12.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 57 +++---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 1 +
2 files changed, 24 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_
Only one interface is responsible for the conversion.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 136 +++--
1 file changed, 59 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0
NPS mode is introduced, the value of memory physical address (PA)
related to a MCA address varies per nps mode. We need to rely on
MCA address and convert it into PA accroding to nps mode.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 97 ++---
1 file
And change some UMC v12 specific functions to generic version, so the
code can be shared.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 63 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 11 +
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 62 ++---
On 11/19/2024 12:34 PM, Kenneth Feng wrote:
> skip the power source check on smu v14.0.2/3
>
> Signed-off-by: Kenneth Feng
Should the commit message be 'Skip setting power source'?
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1 -
>
skip the power source check on smu v14.0.2/3
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index
[AMD Official Use Only - AMD Internal Distribution Only]
The series is: Acked-by: Tao Zhou
> -Original Message-
> From: Lazar, Lijo
> Sent: Friday, November 15, 2024 4:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Zhou1, Tao
> Subject: [PATCH 1
Remove unnecessary variable and simplify the logic.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 76c
Tell the function if the error records come from eeprom.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git
We can set UMC node instance to invalid state if we use global channel index,
and RAS TA can choose UMC address conversion approach by checking node_inst
value.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/d
Convert UMC address via node instance, UMC instance and channel
instance. IPID is not sotred on eeprom, so we have to get related
values in new way, can work in any nps mode.
v2: input mca address for get_die_id_from_pa interface.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ra
The shift bit of PA varys according to NPS mode due to
different address format.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/umc
The function handles one page in one time, allocating umc.retire_unit
bad page records is enough.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm
v1 (legacy way): store channel index within a UMC instance in eeprom
v2: store global channel index in eeprom
V2: only save the flag on eeprom, clear it after saving.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 11 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_u
And implement it for UMC v12_0. The die id is calculated from IPID
register in bad page retirement flow, but we don't store it on eeprom
and it can be also gotten from physical address.
v2: get PA_C4 and PA_R13 from MCA address since they may be cleared in
retired page.
Signed-off-by: Tao Zhou
-
So eeprom space can be saved, compatible with legacy way.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 35 +++--
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgp
So the code can be simplified, and no need to expose the detail of PA
format outside address conversion.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 5 -
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/d
And the function can be reused across amdgpu driver.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 37 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 ++
2 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/am
There are some changes in format of memory normalized address per
NPS mode, need to adjust bit mapping according to NPS mode.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 64 +-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 11 +
2 files changed, 52
One UMC MCA address could map to multiply physical address (PA):
AMDGPU_RAS_EEPROM_REC_PA: one record store one PA
AMDGPU_RAS_EEPROM_REC_MCA: one record store one MCA address, PA
is not cared about
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 33 +++---
So upper layer can return failure directly if address conversion fails.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 19 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 +-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 12
3 files changed, 22 in
disable pcie speed switching on Intel platform for smu v14.0.2/3
based on Intel's requirement.
v2: align the setting with smu v13.
Signed-off-by: Kenneth Feng
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 26 ---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git
On 11/19/2024 11:18 AM, Kenneth Feng wrote:
> skip the power source check on smu v14.0.2/3
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> b/d
From: "jesse.zh...@amd.com"
This reverts commit 10aec8943bcc5123288ded8c97e78312bcf17fb1.
the dev->unplugged flag will also be set to true ,
Only uninstall the driver by amdgpu_exit, not actually unplug the device.
that will cause a new issue.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Kenneth Feng
Sent: Monday, November 18, 2024 16:01
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Feng, Kenneth
Subject: [PATCH] d
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Kenneth Feng
Sent: Tuesday, November 19, 2024 13:48
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Feng, Kenneth
Subject: [PATCH] drm/amdgpu/pm: skip the power source check on smu v14.0.2/3
ski
skip the power source check on smu v14.0.2/3
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 5460f8e62264.
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Kenneth Feng
Sent: Tuesday, November 19, 2024 11:13
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Feng, Kenneth
Subject: [PATC
Nov 18 18:37:33.973691 discernment.aesgi.com kernel: warning:
`QSampleCache::L' uses wireless extensions which will stop working for
Wi-Fi 7 hardware; use nl80211
Nov 18 18:37:35.761857 discernment.aesgi.com kernel: [ cut here
]
Nov 18 18:37:35.761928 discernment.aesgi.com k
On 15/11/24 10:37, Raag Jadav wrote:
> Now that we have device wedged event provided by DRM core, make use
> of it and support both driver rebind and bus-reset based recovery.
> With this in place, userspace will be notified of wedged device on
> gt reset failure.
>
> Signed-off-by: Raag Jadav
>
On 11/18/2024 1:31 PM, Kenneth Feng wrote:
> disable pcie speed switching on Intel platform for smu v14.0.2/3
> based on Intel's requirement.
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 8
> 1 file changed, 8 insertions(+)
>
> diff
On 15/11/24 10:37, Raag Jadav wrote:
> This was previously attempted as xe specific reset uevent but dropped
> in commit 77a0d4d1cea2 ("drm/xe/uapi: Remove reset uevent for now")
> as part of refactoring.
>
> Now that we have device wedged event provided by DRM core, make use
> of it and support
add gen5 display to the user on smu v14.0.2/3
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 8 ++--
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/
[AMD Official Use Only - AMD Internal Distribution Only]
I would change the message slightly. See below. But either way this patch is
Reviewed-by: Harish Kasiviswanathan
-Original Message-
From: amd-gfx On Behalf Of Xiaogang.Chen
Sent: Tuesday, November 12, 2024 1:26 PM
To: amd-gfx@lis
[AMD Official Use Only - AMD Internal Distribution Only]
Hi all,
This week this patchset was tested on 4 systems, two dGPU and two APU based,
and tested across multiple display and connection types.
APU
* Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
* Singl
As part of the suspend sequence VRAM needs to be evicted on dGPUs.
In order to make suspend/resume more reliable we moved this into
the pmops prepare() callback so that the suspend sequence would fail
but the system could remain operational under high memory usage suspend.
Another class of issues
Le 15/11/2024 à 22:09, Dmitry Baryshkov a écrit :
The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
accept const struct drm_display_mode argument. Change the mode_valid
callback of drm_connector to also accept const argument.
Signed-off-by: Dmitry Baryshkov
---
Hi Dmitry,
On Sun, 17 Nov 2024 at 22:54, Laurent Pinchart
wrote:
>
> Hi Dmitry,
>
> Thank you for the patch.
>
> On Fri, Nov 15, 2024 at 11:09:26PM +0200, Dmitry Baryshkov wrote:
> > The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
> > accept const struct drm_display_mode argument. Change t
Make hda_get_mode_idx() accept const struct drm_display_mode pointer
instead of just raw struct drm_display_mode. This is a preparation to
converting the mode_valid() callback of drm_connector to accept const
struct drm_display_mode argument.
Signed-off-by: Dmitry Baryshkov
---
Hi Dmitry,
On Mon, Nov 18, 2024 at 12:35 AM Lijo Lazar wrote:
>
> Write pointer could be 32-bit or 64-bit. Use the correct size during
> initialization.
>
> Signed-off-by: Lijo Lazar
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
> 1 file changed, 1 insertion(+), 1
On Mon, Nov 18, 2024 at 12:57 PM Mario Limonciello
wrote:
>
> There is a strapping issue on NBIO 7.11.x that can lead to spurious PME
> events while in the D0 state.
>
> Signed-off-by: Mario Limonciello
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 9 +
There is a strapping issue on NBIO 7.11.x that can lead to spurious PME
events while in the D0 state.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
b/drivers/gpu/d
Earlier ASICs have strap information exported, and this is missing
for NBIO 7.11.0.
Fixes: ca8c68142ad81 ("drm/amdgpu: add nbio 7.11 registers")
Signed-off-by: Mario Limonciello
---
.../amd/include/asic_reg/nbio/nbio_7_11_0_offset.h | 2 ++
.../amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h |
Applied both.
Thanks!
Alex
On Thu, Nov 14, 2024 at 3:29 AM Chung, ChiaHsuan (Tom)
wrote:
>
> Reviewed-by: Tom Chung
>
> On 11/5/2024 10:01 PM, Zicheng Qu wrote:
> > This commit addresses a null pointer dereference issue in
> > hwss_setup_dpp(). The issue could occur when pipe_ctx->plane_state
Before commit ca47518663973 ("drm/amd: Don't allow s0ix on APUs
older than Raven") there were combinations allowed where a user could
attempt to put a device into s2idle even if the platform was misconfigured.
The idea was just skip the whole amdgpu suspend and resume sequence. This
however doesn
In the case of RAS err_event_athub, the VCPU buffers are corrupted and
cannot be restored in amdgpu_vcn_resume(), the buffers are cleared to
0 for good. However, the firmware flags stored in the buffers need to be
reset, or the firmware cannot work properly.
Signed-off-by: Xiang Liu
---
drivers/
Applied. Thanks!
Alex
On Sat, Nov 16, 2024 at 4:51 AM Steven 'Steve' Kendall
wrote:
>
> On several HP models (tested on HP 3125 and HP Probook 455 G2),
> spurious unplug events are emitted upon login on Chrome OS.
> This is likely due to the way Chrome OS restarts graphics
> upon login, so it's
Applied. Thanks!
Alex
On Mon, Nov 18, 2024 at 6:25 AM Christian König
wrote:
>
> Am 15.11.24 um 18:26 schrieb Christophe JAILLET:
> > 'struct pci_device_id' is not modified in this driver.
> >
> > Constifying this structure moves some data to a read-only section, so
> > increase overall securit
Applied. Thanks.
Alex
On Fri, Nov 15, 2024 at 8:19 PM Huacai Chen wrote:
>
> Clang on LoongArch (18+) appears to be unaffected by the bug causing
> excessive stack usage in calculate_bandwidth(). But when building DC_FP
> support the stack frame size can be as large as 2816 bytes, which causes
[Public]
> From: Tvrtko Ursulin
> Sent: Monday, November 11, 2024 5:30
> On 10/11/2024 15:41, Yunxiang Li wrote:
> > Make drm-active- optional just like drm-resident- and drm-purgeable-.
>
> As Jani has already commented the commit message needs some work.
>
> > Signed-off-by: Yunxiang Li
> > CC
[Public]
Indeed I have, thanks for the reminder
Teddy
On 15/11/24 10:37, Raag Jadav wrote:
> Introduce device wedged event, which notifies userspace of 'wedged'
> (hanged/unusable) state of the DRM device through a uevent. This is
> useful especially in cases where the device is no longer operating as
> expected and has become unrecoverable from dri
[Public]
> From: Tvrtko Ursulin
> Sent: Monday, November 18, 2024 9:38
> On 16/11/2024 04:44, Yunxiang Li wrote:
> > Define how to handle buffers with multiple possible placement so we
> > don't get incompatible implementations. Callout the resident
> > requirement for drm-purgeable- explicitly.
On Mon, Nov 18, 2024 at 3:04 AM Kenneth Feng wrote:
>
> disable pcie speed switching on Intel platform for smu v14.0.2/3
> based on Intel's requirement.
>
> Signed-off-by: Kenneth Feng
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 8
> 1 file c
On 11/18/2024 06:52, Melissa Wen wrote:
On 14/11/2024 16:04, Mario Limonciello wrote:
Although it's really useful information for AMD people, the Jira
shouldn't be in the "title" of the commit message.
"If" we want to get into the habit of including this information for
display code we sho
If user-provided fan speed is higher than max speed, ->set_fan_speed_rpm() won't
return error code, which can lead not only to problems with the hardware, but
also to a zero division in smu_v13_0_set_fan_speed_rpm, since (8 * speed), which
is used as a divisor, can evaluate to zero because of an in
On 16/11/2024 04:44, Yunxiang Li wrote:
When memory stats is generated fresh everytime by going though all the
BOs, their active information is quite easy to get. But if the stats are
tracked with BO's state this becomes harder since the job scheduling
part doesn't really deal with individual b
Am 16.11.24 um 05:44 schrieb Yunxiang Li:
Define how to handle buffers with multiple possible placement so we
don't get incompatible implementations. Callout the resident requirement
for drm-purgeable- explicitly. Remove the requirement for there to be
only drm-memory- or only drm-resident-, it's
Write pointer could be 32-bit or 64-bit. Use the correct size during
initialization.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/am
On Mon, Nov 18, 2024 at 11:26:03AM +0200, Jani Nikula wrote:
> On Mon, 18 Nov 2024, Dmitry Baryshkov wrote:
> > On Mon, 18 Nov 2024 at 01:33, Laurent Pinchart
> > wrote:
> >>
> >> On Mon, Nov 18, 2024 at 01:22:12AM +0200, Dmitry Baryshkov wrote:
> >> > On Sun, 17 Nov 2024 at 22:54, Laurent Pincha
In SRIOV, when host driver performs MODE 1 reset and notifies FLR to
guest driver, there is a small chance that there is no job running on hw
but the driver has not updated the pending list yet, causing the driver
not respond the FLR request. Modify the has_job_running function to
make sure if ther
Fix the similar warning when hotplugging:
[ 155.585721] kernfs: can not remove 'enforce_isolation', no directory
[ 155.592201] WARNING: CPU: 3 PID: 6960 at fs/kernfs/dir.c:1683
kernfs_remove_by_name_ns+0xb9/0xc0
[ 155.601145] Modules linked in: xt_MASQUERADE xt_comment nft_compat veth
bridge
On 14/11/2024 16:04, Mario Limonciello wrote:
Although it's really useful information for AMD people, the Jira
shouldn't be in the "title" of the commit message.
"If" we want to get into the habit of including this information for
display code we should come up with a prescriptive field th
On Mon, Nov 18, 2024 at 11:26:03AM +0200, Jani Nikula wrote:
> On Mon, 18 Nov 2024, Dmitry Baryshkov wrote:
> > On Mon, 18 Nov 2024 at 01:33, Laurent Pinchart wrote:
> >> On Mon, Nov 18, 2024 at 01:22:12AM +0200, Dmitry Baryshkov wrote:
> >> > On Sun, 17 Nov 2024 at 22:54, Laurent Pinchart wrote:
>
On Fri, Nov 15, 2024 at 11:09:30PM +0200, Dmitry Baryshkov wrote:
> The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
> accept const struct drm_display_mode argument. Change the mode_valid
> callback of drm_connector to also accept const argument.
>
> Signed-off-by: Dmitry Baryshk
Am 15.11.24 um 18:26 schrieb Christophe JAILLET:
'struct pci_device_id' is not modified in this driver.
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig:
Before:
==
text data bss dec hex
Am 18.11.24 um 05:31 schrieb jesse.zh...@amd.com:
Replace the check drm_dev_enter with sysfs directory entry.
Because the dev->unplugged flag will also be set to true,
Only uninstall the driver by amdgpu_exit, not actually unplug the device.
Clearly a NAK to this one. This looks strongly like y
On Fri, 15 Nov 2024, Dmitry Baryshkov wrote:
> The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
> accept const struct drm_display_mode argument. Change the mode_valid
> callback of drm_connector to also accept const argument.
>
> Signed-off-by: Dmitry Baryshkov
Acked-by: Jani N
On Fri, 15 Nov 2024, Dmitry Baryshkov wrote:
> The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge
> accept const struct drm_display_mode argument. Change the mode_valid_ctx
> callback of drm_connector to also accept const argument.
>
> Signed-off-by: Dmitry Baryshkov
Acked-by: Ja
On Mon, 18 Nov 2024, Dmitry Baryshkov wrote:
> On Mon, 18 Nov 2024 at 01:33, Laurent Pinchart
> wrote:
>>
>> On Mon, Nov 18, 2024 at 01:22:12AM +0200, Dmitry Baryshkov wrote:
>> > On Sun, 17 Nov 2024 at 22:54, Laurent Pinchart wrote:
>> > > On Fri, Nov 15, 2024 at 11:09:26PM +0200, Dmitry Baryshk
On 11/16/2024 7:32 PM, Alex Deucher wrote:
> smu->workload_mask is IP specific and should not be messed with in
> the common code. The mask bits vary across SMU versions.
>
> Move all handling of smu->workload_mask in to the backends and
> simplify the code. Store the user's preference in smu-
On Mon, 30 Sep 2024 13:20:46 +0200, Julia Lawall wrote:
> Reorganize kerneldoc parameter names to match the parameter
> order in the function header.
>
> The misordered cases were identified using the following
> Coccinelle semantic patch:
>
> //
> @initialize:ocaml@
> @@
>
> [...]
Applied to
disable pcie speed switching on Intel platform for smu v14.0.2/3
based on Intel's requirement.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
b/
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