[PATCH] drm/amd/pm: fix and simplify workload handling

smu->workload_mask is IP specific and should not be messed with in the common code. The mask bits vary across SMU versions. Move all handling of smu->workload_mask in to the backends and simplify the code. Store the user's preference in smu->power_profile_mode which will be reflected in sysfs. F

[PATCH v4 2/2] drm/display/dsc: MST DSC Interface Change

[why] Starting from dp2 where dsc passthrough is introduced, it is required to identify the dsc passthrough aux, apart from dsc decompression aux. Existing drm_dp_mst_port function that returns dsc_aux alone is not sufficient. [how] 1. Interface change in drm_dp_mst_dsc_aux_for_port, and depende

[PATCH v4 0/2] Refactor MST DSC Determination Policy

The patch series is to refactor existing dsc determination policy for dsc decompression and dsc passthrough given a mst output port. Original routine was written based on different peer device types which is not accurate and shows difficulty when expanding support of products that do not fully com

[PATCH v4 1/2] drm/display/dsc: Refactor DRM MST DSC Determination Policy

[why] How we determine the dsc_aux used for dsc decompression in drm_dp_mst_dsc_aux_for_port() today has defects: 1. The method how we determine a connected peer device is virtual or not in drm_dp_mst_is_virtual_dpcd() is not always correct. There are DP1.4 products in the market which don'

Re: [PATCH-next v3] drm/amdgpu: Cleanup shift coding style

Applied. Thanks! Sorry for the delay. Alex On Fri, Nov 8, 2024 at 10:11 AM Advait Dhamorikar wrote: > > Hello, > > I have addressed the previous comments, > Is there something more that I need to address in this version of the patch? > I would appreciate feedback. > > Best regards, > Advait >

[PATCH 2/2] Revert "drm/amd/display: parse umc_info or vram_info based on ASIC"

This reverts commit 2551b4a321a68134360b860113dd460133e856e5. This was not the root cause. Revert. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3678 Signed-off-by: Alex Deucher Cc: aurabindo.pil...@amd.com Cc: hamishclax...@gmail.com --- drivers/gpu/drm/amd/display/dc/bios/bios_parser

[PATCH 1/2] drm/amd/display: Fix failure to read vram info due to static BP_RESULT

From: Hamish Claxton The static declaration causes the check to fail. Remove it. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3678 Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by: Hamish Claxton Signed-off-by: Alex Deucher Cc: aurabindo.pil...@

Re: [PATCH 6.6 00/28] fix CVE-2024-46701

> On Nov 7, 2024, at 8:19 PM, Yu Kuai wrote: > > Hi, > > 在 2024/11/07 22:41, Chuck Lever 写道: >> On Thu, Nov 07, 2024 at 08:57:23AM +0800, Yu Kuai wrote: >>> Hi, >>> >>> 在 2024/11/06 23:19, Chuck Lever III 写道: > On Nov 6, 2024, at 1:16 AM, Greg KH wrote: > > On Thu, O

[PATCH 6.1 resend] Revert "drm/amd/display: Skip Recompute DSC Params if no Stream on Link"

This reverts commit 7c887efda1201110211fed8921a92a713e0b6bcd which is commit 8151a6c13111b465dbabe07c19f572f7cbd16fef upstream. It is a duplicate of the change made in 6.1.105 by commit 282f0a482ee6 ("drm/amd/display: Skip Recompute DSC Params if no Stream on Link"). This is a consequence of two

Re: [PATCH 2/2] drm/amdkfd: use cache GTT buffer for PQ and wb pool

Am 08.11.24 um 12:26 schrieb Lazar, Lijo: On 11/8/2024 4:29 PM, Liu, Monk wrote: [AMD Official Use Only - AMD Internal Distribution Only] To be clear for the mb() approach: Even if we insert mb() in prior to amdgpu_ring_set_wptr(ring), GPU might still fetch stalled data from PQ due to USWC at

Re: [PATCH 4/5] drm/amd/display: add DC drm_panic support

On 2024-11-05 09:06, Alex Deucher wrote: > From: Jocelyn Falempe > > Add support for the drm_panic module, which displays a pretty user > friendly message on the screen when a Linux kernel panic occurs. > > It doesn't work yet on laptop panels, maybe due to PSR. > > Adapted from Jocelyn's or

Re: [PATCH 01/23] drm/amdgpu: add flag to indicate nps mode switch

On 11/8/2024 4:44 PM, Tao Zhou wrote: > There are two types of gpu reset, nps mode switch and normal > gpu reset, add a flag to distigush them. > Reset for NPS switch is a subcase of Reset on Initialization scenario (reset the device before use). If RAS routines need to be taken care for that

Re: [PATCH 2/2] drm/amdkfd: use cache GTT buffer for PQ and wb pool

On 11/8/2024 4:29 PM, Liu, Monk wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > > To be clear for the mb() approach: Even if we insert mb() in prior to > amdgpu_ring_set_wptr(ring), GPU might still fetch stalled data from PQ due to > USWC attributes. > Inserting an mb() d

[PATCH 19/23] drm/amdgpu: add ras_mca2pa to convert UMC address in legacy way

Convert UMC address via node instance, UMC instance and channel instance. IPID is not sotred on eeprom, so we have to get related values in new way, can work in any nps mode. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 41 +++-- 1 file changed, 39 in

[PATCH 13/23] drm/amdgpu: retire RAS bad pages in different NPS modes

There are some changes in format of memory normalized address per NPS mode, need to adjust bit mapping according to NPS mode. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 64 +- drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 11 + 2 files changed, 52

[PATCH 17/23] drm/amdgpu: add a flag to indicate UMC channel index version

v1 (legacy way): store channel index within a UMC instance in eeprom v2: store global channel index in eeprom Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 + drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 16 2 files changed, 25 insertions(+) diff

[PATCH 21/23] drm/amdgpu: parse legacy RAS bad page mixed with new data in various NPS modes

All legacy RAS bad pages are generated in NPS1 mode, but new bad page can be generated in any NPS mode, so we can't use retired_page sotred on eeprom directly in non-nps1 mode even for legacy data. We need to take different actions for different data, new data can be identified from old data by UMC

[PATCH 07/23] drm/amdgpu: reduce memory usage for umc_lookup_bad_pages_in_a_row

The function handles one page in one time, allocating umc.retire_unit bad page records is enough. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm

[PATCH 15/23] drm/amdgpu: support to find RAS bad pages via old TA

Old version of RAS TA doesn't support to convert MCA address to physical address (PA), support to find all bad pages in one memory row by PA with old RAS TA. This approach is only suitable for nps1 mode. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 26 +++

[PATCH 22/23] drm/amdgpu: remove is_mca_add for ras_add_bad_pages

Remove unnecessary variable and simplify the logic. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 +++--- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 324

[PATCH 14/23] drm/amdgpu: add function to find all memory pages in one physical row

And the function can be reused across amdgpu driver. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 37 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 ++ 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/am

[PATCH 20/23] drm/amdgpu: add from_rom parameter for ras_add_bad_pages

Tell the function if the error records come from eeprom. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git

[PATCH 23/23] drm/amdgpu: set UMC PA per NPS mode when PA is 0

The shift bit of PA varys according to NPS mode due to different address format. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc

[PATCH 05/23] drm/amdgpu: store PA with column bits cleared for RAS bad page

So the code can be simplified, and no need to expose the detail of PA format outside address conversion. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 4 +++- drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 5 - 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/d

[PATCH 18/23] drm/amdgpu: add interface to get die id from memory address

And implement it for UMC v12_0. The die id calculated from IPID register in bad page retirement, but we don't store it on eeprom and it can be also gotten from physical address. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 ++ drivers/gpu/drm/amd/amdgpu/umc_v12_0.c |

[PATCH 04/23] drm/amdgpu: remove redundant RAS error address coversion code

Only one interface is responsible for the conversion. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 136 +++-- 1 file changed, 59 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0

[PATCH 16/23] drm/amdgpu: save UMC global channel index to eeprom

Save the global channel index returned by RAS TA to eeprom. We can get memory physical address by MCA address and channel index. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 7 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_um

[PATCH 12/23] drm/amdgpu: store only one RAS bad page record for all pages in one row

So eeprom space can be saved, compatible with legacy way. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 35 +++-- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgp

[PATCH 10/23] drm/amdgpu: add flag to indicate the type of RAS eeprom record

One UMC MCA address could map to multiply physical address (PA): AMDGPU_RAS_EEPROM_REC_PA: one record store one PA AMDGPU_RAS_EEPROM_REC_MCA: one record store one MCA address, PA is not cared about Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 33 +++---

[PATCH 11/23] drm/amdgpu: do RAS MCA2PA conversion in initial phase

NPS mode is introduced, the value of memory physical address (PA) related to a MCA address varies per nps mode. We need to rely on MCA address and convert it into PA accroding to nps mode. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 97 ++--- 1 file

[PATCH 03/23] drm/amdgpu: simplify RAS page retirement in one memory row

Take R13 and column bits as a whole for UMC v12. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 57 +++--- drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 1 + 2 files changed, 24 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_

[PATCH 09/23] drm/amdgpu: add TA_RAS_INV_NODE value

We can set UMC node instance to invalid state if we use global channel index, and RAS TA can choose UMC address conversion approach by checking node_inst value. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/ta_ras_if.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/d

[PATCH 08/23] drm/amdgpu: add return value for convert_ras_err_addr

So upper layer can return failure directly if address conversion fails. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 19 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 +- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 12 3 files changed, 22 in

[PATCH 06/23] drm/amdgpu: make convert_ras_err_addr visible outside UMC block

And change some UMC v12 specific functions to common version, so the code can be shared. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 63 + drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 11 + drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 62 ++

[PATCH 01/23] drm/amdgpu: add flag to indicate nps mode switch

There are two types of gpu reset, nps mode switch and normal gpu reset, add a flag to distigush them. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 13

[PATCH 02/23] drm/amdgpu: do RAS init in NPS mode switch

NPS mode switch will call gpu reset, but this is different from normal reset. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 11 +++ 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/dr

RE: [PATCH 2/2] drm/amdkfd: use cache GTT buffer for PQ and wb pool

[AMD Official Use Only - AMD Internal Distribution Only] To be clear for the mb() approach: Even if we insert mb() in prior to amdgpu_ring_set_wptr(ring), GPU might still fetch stalled data from PQ due to USWC attributes. The issue here is not the re-ordering but the stalled PQ. Monk Liu | Clo

Re: [PATCH 2/2] drm/amdkfd: use cache GTT buffer for PQ and wb pool

On 11/8/2024 3:51 PM, Liu, Monk wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > > Christian/Lijo > > We verified all approaches, and we know what works and not works, obviously > the mb() doesn't work. > > The way of mb() between set wptr_polling and kicking off doorbell

RE: [PATCH 2/2] drm/amdkfd: use cache GTT buffer for PQ and wb pool

[AMD Official Use Only - AMD Internal Distribution Only] Christian/Lijo We verified all approaches, and we know what works and not works, obviously the mb() doesn't work. The way of mb() between set wptr_polling and kicking off doorbell is theoretically correct, and I'm not object to do so...

[PATCH V2] drm/amdgpu: fix warning when removing sysfs

Fix the similar warning: [ 155.585721] kernfs: can not remove 'enforce_isolation', no directory [ 155.592201] WARNING: CPU: 3 PID: 6960 at fs/kernfs/dir.c:1683 kernfs_remove_by_name_ns+0xb9/0xc0 [ 155.601145] Modules linked in: xt_MASQUERADE xt_comment nft_compat veth bridge stp llc overlay n

Re: [PATCH v2 05/10] sysfs: treewide: constify attribute callback of bin_is_visible()

On 03/11/2024 17:03, Thomas Weißschuh wrote: The is_bin_visible() callbacks should not modify the struct bin_attribute passed as argument. Enforce this by marking the argument as const. As there are not many callback implementers perform this change throughout the tree at once. Signed-off-by

Re: [PATCH v2 04/10] nvmem: core: calculate bin_attribute size through bin_size()

On 03/11/2024 17:03, Thomas Weißschuh wrote: Stop abusing the is_bin_visible() callback to calculate the attribute size. Instead use the new, dedicated bin_size() one. Signed-off-by: Thomas Weißschuh --- Thanks for the patch, LGTM. Acked-by: Srinivas Kandagatla --srini drivers/nvmem

RE: [PATCH] drm/amdgpu: fix warning when removing sysfs

[AMD Official Use Only - AMD Internal Distribution Only] Hi Lijo, -Original Message- From: Lazar, Lijo Sent: Friday, November 8, 2024 5:24 PM To: Zhang, Jesse(Jie) ; Koenig, Christian ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Prosyak, Vitaly ; Huang, Tim Subject: Re: [PA

Re: [PATCH] drm/amdkfd: correct the SVM DMA device unmap direction

Am 08.11.24 um 10:15 schrieb Liang, Prike: [AMD Official Use Only - AMD Internal Distribution Only] From: Koenig, Christian Sent: Wednesday, November 6, 2024 8:24 PM To: Kuehling, Felix ; Liang, Prike ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Kasiviswanathan, Harish Subject: Re

RE: [PATCH] drm/amdgpu: fix warning when removing sysfs

[AMD Official Use Only - AMD Internal Distribution Only] Hi Christian, -Original Message- From: Koenig, Christian Sent: Friday, November 8, 2024 3:51 PM To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Prosyak, Vitaly ; Huang, Tim Subject: Re: [PATCH] drm/

Re: [PATCH] drm/amdgpu: fix warning when removing sysfs

On 11/8/2024 2:45 PM, Zhang, Jesse(Jie) wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Christian, > > -Original Message- > From: Koenig, Christian > Sent: Friday, November 8, 2024 3:51 PM > To: Zha

RE: [PATCH] drm/amdkfd: correct the SVM DMA device unmap direction

[AMD Official Use Only - AMD Internal Distribution Only] > From: Koenig, Christian > Sent: Wednesday, November 6, 2024 8:24 PM > To: Kuehling, Felix ; Liang, Prike > ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Kasiviswanathan, Harish > > Subject: Re: [PATCH] drm/amdkfd: correct th

Re: [PATCH 6.6 00/28] fix CVE-2024-46701

Hi, 在 2024/11/07 22:41, Chuck Lever 写道: On Thu, Nov 07, 2024 at 08:57:23AM +0800, Yu Kuai wrote: Hi, 在 2024/11/06 23:19, Chuck Lever III 写道: On Nov 6, 2024, at 1:16 AM, Greg KH wrote: On Thu, Oct 24, 2024 at 09:19:41PM +0800, Yu Kuai wrote: From: Yu Kuai Fix patch is patch 27, relied

Re: [PATCH 6.6 00/28] fix CVE-2024-46701

On Thu, Nov 07, 2024 at 08:57:23AM +0800, Yu Kuai wrote: > Hi, > > 在 2024/11/06 23:19, Chuck Lever III 写道: > > > > > > > On Nov 6, 2024, at 1:16 AM, Greg KH wrote: > > > > > > On Thu, Oct 24, 2024 at 09:19:41PM +0800, Yu Kuai wrote: > > > > From: Yu Kuai > > > > > > > > Fix patch is patch 27

Re: [PATCH 0/1] On DRM -> stable process

On Fri, Nov 08, 2024 at 11:41:18AM +0300, Fedor Pchelkin wrote: > On Tue, 05. Nov 07:57, Greg Kroah-Hartman wrote: > > On Mon, Nov 04, 2024 at 05:55:28PM +0300, Fedor Pchelkin wrote: > > > It is just strange that the (exact same) change made by the commits is > > > duplicated by backporting tools.

Re: [PATCH v6 5/5] drm/amdgpu: track bo memory stats at runtime

On 07/11/2024 14:24, Li, Yunxiang (Teddy) wrote: [Public] From: Tvrtko Ursulin Sent: Thursday, November 7, 2024 5:48 On 31/10/2024 13:48, Li, Yunxiang (Teddy) wrote: [Public] From: Christian König Sent: Thursday, October 31, 2024 8:54 Am 25.10.24 um 19:41 schrieb Yunxiang Li: Before, ev

Re: [PATCH v6 4/5] drm: add drm_memory_stats_is_zero

On 07/11/2024 14:17, Li, Yunxiang (Teddy) wrote: [AMD Official Use Only - AMD Internal Distribution Only] From: Tvrtko Ursulin Sent: Thursday, November 7, 2024 5:41 On 25/10/2024 18:41, Yunxiang Li wrote: Add a helper to check if the memory stats is zero, this will be used to check for memo

Re: [PATCH 6.6 00/28] fix CVE-2024-46701

* Yu Kuai [241106 19:57]: > Hi, > > 在 2024/11/06 23:19, Chuck Lever III 写道: > > > > > > > On Nov 6, 2024, at 1:16 AM, Greg KH wrote: > > > > > > On Thu, Oct 24, 2024 at 09:19:41PM +0800, Yu Kuai wrote: > > > > From: Yu Kuai > > > > > > > > Fix patch is patch 27, relied patches are from: > >

Re: [PATCH 0/1] On DRM -> stable process

On Tue, 05. Nov 07:57, Greg Kroah-Hartman wrote: > On Mon, Nov 04, 2024 at 05:55:28PM +0300, Fedor Pchelkin wrote: > > It is just strange that the (exact same) change made by the commits is > > duplicated by backporting tools. As it is not the first case where DRM > > patches are involved per Greg'

[PATCH Review 1/1] drm/amdgpu: Support vcn and jpeg error info parsing

Add vcn and jpeg error count parsing. Signed-off-by: Stanley.Yang Reviewed-by: Yang Wang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 24 +++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/sws