On 11/6/2024 12:34 AM, Victor Skvortsov wrote:
> Enable RAS late init if VF RAS Telemetry is supported.
>
> When enabled, the VF can use this interface to query total
> RAS error counts from the host.
>
> The VF FB access may abruptly end due to a fatal error,
> therefore the VF must cache an
Correct kiq unmap queue timeout value.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 9d0e342a2f81..1ce935e684c7 100644
On 11/6/2024 8:42 PM, Alex Deucher wrote:
> On Wed, Nov 6, 2024 at 1:49 AM Victor Zhao wrote:
>>
>> From: Monk Liu
>>
>> As cache GTT buffer is snooped, this way the coherence between CPU write
>> and GPU fetch is guaranteed, but original code uses WC + unsnooped for
>> HIQ PQ(ring buffer) whi
On Thu, Nov 07, 2024 at 05:05:13AM +0900, Krzysztof Wilczyński wrote:
> Hello,
>
> > Several drivers need to dynamically calculate the size of an binary
> > attribute. Currently this is done by assigning attr->size from the
> > is_bin_visible() callback.
> >
> > This has drawbacks:
> > * It is no
On 2024/11/6 23:50, Christian König wrote:
> Am 06.11.24 um 04:20 schrieb Chen, Jiqian:
>> On 2024/11/5 21:42, Christian König wrote:
>>> Am 05.11.24 um 07:05 schrieb Jiqian Chen:
VPCI of Xen doesn't support resizable bar. When discrete GPU is used on
PVH dom0 which using the VPCI, amdgpu
On 2024-11-06 17:54, Ramesh Errabolu wrote:
> Raise an info message in kernel log if PCIe root complex
> determines that a AMD GPU device D cannot have P2P
> communication with another AMD GPU device D
>
> Signed-off-by: Ramesh Errabolu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
Raise an info message in kernel log if PCIe root complex
determines that a AMD GPU device D cannot have P2P
communication with another AMD GPU device D
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu
[AMD Official Use Only - AMD Internal Distribution Only]
Good suggestion.
This message should only print when the two devices (provider and client) are:
- Not behind the same root complex
- The host bridge connecting them is not whitelisted
Will update patch and post it for review
Regards,
On 2024-11-05 20:19, Ramesh Errabolu wrote:
> Raise an info message in kernel log if PCIe root complex
> determines that a AMD GPU device D cannot have P2P
> communication with another AMD GPU device D
>
> Signed-off-by: Ramesh Errabolu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
On 2024-11-05 20:35, Yuan Can wrote:
> In kfd_procfs_show(), the sdma_activity_work_handler is a local variable
> and the sdma_activity_work_handler.sdma_activity_work should initialize
> with INIT_WORK_ONSTACK() instead of INIT_WORK().
>
> Fixes: 32cb59f31362 ("drm/amdkfd: Track SDMA utilization
On 11/5/2024 14:22, Hamza Mahfooz wrote:
From: Tom Chung
[Why]
In certain use case such as KDE login screen, there will be no atomic
commit while do the frame update.
If the Panel Replay enabled, it will cause the screen not updated and
looks like system hang.
[How]
Delay few atomic commits be
Hello,
> Several drivers need to dynamically calculate the size of an binary
> attribute. Currently this is done by assigning attr->size from the
> is_bin_visible() callback.
>
> This has drawbacks:
> * It is not documented.
> * A single attribute can be instantiated multiple times, overwriting t
Am 03.11.24 um 18:03 schrieb Thomas Weißschuh:
Several drivers need to dynamically calculate the size of an binary
attribute. Currently this is done by assigning attr->size from the
is_bin_visible() callback.
Hi,
i really like your idea of introducing this new callback, it will be very
useful
On 11/5/2024 6:31 PM, Felix Kuehling wrote:
On 2024-10-28 17:40, Xiaogang.Chen wrote:
From: Xiaogang Chen
To allow user better understand the cause triggering runlist
oversubscription.
No function change.
Signed-off-by: Xiaogang Chen xiaogang.c...@amd.com
---
.../gpu/drm/amd/amdkfd/kfd
Reviewed-by: Amber Lin
Regards,
Amber
On 2024-11-06 11:08, Amber Lin wrote:
From: Max Erenberg
These options are necessary to use virtio devices with QEMU.
Signed-off-by: Max Erenberg
---
arch/x86/configs/rock-dbg_defconfig | 14 ++
1 file changed, 14 insertions(+)
diff --g
Hi Dave, Simona,
Last few updates for 6.13.
The following changes since commit dac64cb3e029e9ae9ca251798bcb9cdb118d68d5:
drm/amdgpu: Fix amdgpu_ip_block_hw_fini() (2024-10-24 18:07:10 -0400)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-dr
From: Max Erenberg
These options are necessary to use virtio devices with QEMU.
Signed-off-by: Max Erenberg
---
arch/x86/configs/rock-dbg_defconfig | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/configs/rock-dbg_defconfig
b/arch/x86/configs/rock-dbg_defconfig
ind
On Wed, Nov 6, 2024 at 3:18 AM Zicheng Qu wrote:
>
> The current implementation incorrectly updates DOMAIN10_PG_CONFIG with
> DOMAIN8_POWER_FORCEON, which is not the intended behavior. This patch
> corrects the power gating configuration by updating DOMAIN10_PG_CONFIG
> with DOMAIN10_POWER_FORCEON
Am 06.11.24 um 04:20 schrieb Chen, Jiqian:
On 2024/11/5 21:42, Christian König wrote:
Am 05.11.24 um 07:05 schrieb Jiqian Chen:
VPCI of Xen doesn't support resizable bar. When discrete GPU is used on
PVH dom0 which using the VPCI, amdgpu fails to probe, so we need to
disable this capability for
Reviewed-by: Boyuan Zhang
On 2024-11-05 21:09, Srinivasan Shanmugam wrote:
This commit corrects the descriptors for the
vcn_v4_0/v4_0_3/v4_0_5/v5_0_0 _set_clockgating_state and
vcn_v4_0/v4_0_3/v4_0_5/v5_0_0 _set_powergating_state functions in the
amdgpu driver.
The parameter descriptors in the
Reviewed-by: Boyuan Zhang
On 2024-11-05 21:16, Srinivasan Shanmugam wrote:
This commit adds the missing kdoc parameter descriptor for 'inst' in the
smu_dpm_set_power_gate function.
The 'inst' parameter, which specifies the instance of the IP block to
power gate/ungate.
Fixes the below with gc
On Wed, Nov 6, 2024 at 3:24 AM Zicheng Qu wrote:
>
> The current implementation incorrectly updates DOMAIN11_PG_CONFIG with
> DOMAIN9_POWER_FORCEON, which is not the intended behavior. This patch
> corrects the power gating configuration by updating DOMAIN11_PG_CONFIG
> with DOMAIN11_POWER_FORCEON
On Wed, Nov 6, 2024 at 1:49 AM Victor Zhao wrote:
>
> From: Monk Liu
>
> As cache GTT buffer is snooped, this way the coherence between CPU write
> and GPU fetch is guaranteed, but original code uses WC + unsnooped for
> HIQ PQ(ring buffer) which introduces coherency issues:
> MEC fetches a stall
On Wed, Nov 6, 2024 at 1:49 AM Victor Zhao wrote:
>
> From: Gang Ba
>
> amdgpu_amdkfd_alloc_gtt_mem currently allocates USWC memory.
> It uses write-combining for CPU access, which is slow for reading.
> Add a new parameter to amdgpu_amdkfd_alloc_gtt_mem to allocate
> normal GTT memory.
>
> Signe
[why]
How we determine the dsc_aux used for dsc decompression in
drm_dp_mst_dsc_aux_for_port() today has defects:
1. The method how we determine a connected peer device is virtual or not
in drm_dp_mst_is_virtual_dpcd() is not always correct. There are DP1.4
products
in the market which don'
The patch series is to refactor existing dsc determination policy for
dsc decompression and dsc passthrough given a mst output port.
Original routine was written based on different peer device types
which is not accurate and shows difficulty when expanding support of
products that do not fully com
[why]
Starting from dp2 where dsc passthrough is introduced, it is required to
identify
the dsc passthrough aux, apart from dsc decompression aux. Existing
drm_dp_mst_port function
that returns dsc_aux alone is not sufficient.
[how]
1. Interface change in drm_dp_mst_dsc_aux_for_port, and depende
Am 05.11.24 um 17:34 schrieb Felix Kuehling:
On 2024-11-05 06:04, Christian König wrote:
Am 05.11.24 um 03:33 schrieb Prike Liang:
The SVM DMA device unmap direction should be same as
the DMA map process.
At least of hand that looks like it's only papering over a major
problem.
Why are DMA
On Tue, Nov 5, 2024 at 9:19 PM Srinivasan Shanmugam
wrote:
>
> This commit adds the cleaner shader microcode for GFX10.3.0 GPUs. The
> cleaner shader is a piece of GPU code that is used to clear or
> initialize certain GPU resources, such as Local Data Share (LDS), Vector
> General Purpose Registe
In kfd_procfs_show(), the sdma_activity_work_handler is a local variable
and the sdma_activity_work_handler.sdma_activity_work should initialize
with INIT_WORK_ONSTACK() instead of INIT_WORK().
Fixes: 32cb59f31362 ("drm/amdkfd: Track SDMA utilization per process")
Signed-off-by: Yuan Can
---
dri
The current implementation incorrectly updates DOMAIN11_PG_CONFIG with
DOMAIN9_POWER_FORCEON, which is not the intended behavior. This patch
corrects the power gating configuration by updating DOMAIN11_PG_CONFIG
with DOMAIN11_POWER_FORCEON, preventing potential issues related to
power management.
On Thu, Oct 24, 2024 at 09:19:41PM +0800, Yu Kuai wrote:
> From: Yu Kuai
>
> Fix patch is patch 27, relied patches are from:
>
> - patches from set [1] to add helpers to maple_tree, the last patch to
> improve fork() performance is not backported;
So things slowed down?
> - patches from set
The current implementation incorrectly updates DOMAIN10_PG_CONFIG with
DOMAIN8_POWER_FORCEON, which is not the intended behavior. This patch
corrects the power gating configuration by updating DOMAIN10_PG_CONFIG
with DOMAIN10_POWER_FORCEON, preventing potential issues related to
power management.
Hi all,
I am submitting two patches to correct power gating configurations in
the AMD display driver.
1. Patch 1/2 (Fixes: 46825fcfbe16): Corrects DOMAIN10_PG_CONFIG to use
DOMAIN10_POWER_FORCEON.
2. Patch 2/2 (Fixes: 46825fcfbe16): Corrects DOMAIN11_PG_CONFIG to use
DOMAIN11_POWER_FORCEON.
Than
Am Di., 5. Nov. 2024 um 16:16 Uhr schrieb Matias N. Goldberg
:
>
> > That's not a problem, incompatible options can just be rejected in atomic
> > tests.
>
> I was thinking from a user perspective. It'd be easier for user-space config
> apps to present only the valid options, rather than offering
This commit addresses a null pointer dereference issue in
dcn20_program_pipe(). Previously, commit 8e4ed3cf1642 ("drm/amd/display:
Add null check for pipe_ctx->plane_state in dcn20_program_pipe")
partially fixed the null pointer dereference issue. However, in
dcn20_update_dchubp_dpp(), the variable
Hi all,
I am submitting two patches to fix null pointer dereference issues in
the AMD display driver.
1. Patch 1/2 (Fixes: 8e4ed3cf1642): Add null checks in
dcn20_program_pipe() to prevent potential crashes when accessing
plane_state.
2. Patch 2/2 (Fixes: 0baae6246307): Ensures pipe_ctx->plane_s
This commit addresses a null pointer dereference issue in
hwss_setup_dpp(). The issue could occur when pipe_ctx->plane_state is
null. The fix adds a check to ensure `pipe_ctx->plane_state` is not null
before accessing. This prevents a null pointer dereference.
Fixes: 0baae6246307 ("drm/amd/display
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