[AMD Official Use Only - AMD Internal Distribution Only]
Hi Lijo,
Thanks a lot for your review and suggestions.
Here are the updated patches.
Best Regards,
Frank
From: Frank Min
Date: Thu, 10 Oct 2024 16:41:32 +0800
Subject: [PATCH 1/2] drm/amdgpu: fix random data corruption for sdma 7
There
From: Jiadong Zhu
Implement sdma queue reset callback via SMU interface.
v2: Leverage inst_stop/start functions in reset sequence.
Use GET_INST for physical SDMA instance.
Disable apu for sdma reset.
v3: Rephrase error prints.
v4: Remove redundant prints. Remove setting PREEMPT registers
From: Jiadong Zhu
Implement sdma soft reset by sending MSG_ResetSDMA on smu 13.0.6.
v2: Add firmware version for the reset message.
v3: Add ip version check. Print inst_mask on failure.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15
drivers/gpu
From: Jiadong Zhu
update smu header for sdma soft reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu
On 10/16/2024 8:29 AM, Min, Frank wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> From: Frank Min
>
> There is random data corruption caused by const fill, this is caused by write
> compression mode not corre
[AMD Official Use Only - AMD Internal Distribution Only]
From: Frank Min
There is random data corruption caused by const fill, this is caused by write
compression mode not correclt configured.
So correct compression mode for const fill.
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgp
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Jiadong Zhu
> -Original Message-
> From: Deucher, Alexander
> Sent: Wednesday, October 16, 2024 4:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kim, Jonathan
> ; Zhu, Jiadong
> Subject: [PATCH] R
On Tue, Oct 15, 2024 at 3:58 AM Arunpravin Paneer Selvam
wrote:
>
> Drop AMDGPU_USERQ_BO_WRITE as this should not be a global option
> of the IOCTL, It should be option per buffer. Hence adding separate
> array for read and write BO handles.
>
> Signed-off-by: Arunpravin Paneer Selvam
> Acked-by:
From: Xiaogang Chen
The purpose of this patch is having kfd driver function as expected during AMD
gpu device plug/unplug.
When an AMD gpu device got unplug kfd driver stops all queues from this device.
If there are user processes still ref the render node this device is marked as
invalid. kfd d
This reverts commit 7c1a2d8aba6cadde0cc542b2d805edc0be667e79.
Extended validation has completed successfully, so enable
these features by default.
Signed-off-by: Alex Deucher
Cc: Jonathan Kim
Cc: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4
drivers/gpu/drm/amd/a
On Tue, Oct 15, 2024 at 2:23 PM Victor Lu wrote:
>
> Port this change to vega20_ih.c:
> "89ae318001e5 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts"
Might be helpful to quote the commit message here just so it's clear
why that change is needed. With that, the patch is:
Reviewed-by:
Add messages to make it clear when a per ring reset
happens. This is helpful for debugging and aligns with
other reset methods.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
Port this change to vega20_ih.c:
"89ae318001e5 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts"
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 27 ++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
b
[AMD Official Use Only - AMD Internal Distribution Only]
Ping
-Original Message-
From: Liu, Shaoyun
Sent: Friday, October 4, 2024 12:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdkfd: add/remove kfd queues through on stop/start KFD
scheduling
Add bac
For debugging purposes, add a runtime override to disable display scanout
from MALL cache (MALL Static Screen) by disallowing the driver from
triggering the idle power optimizations when desktop is idle.
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++
On 15/10/2024 18:50, Alex Deucher wrote:
On Tue, Oct 15, 2024 at 12:33 PM Shashank Sharma
wrote:
This patch sets MES HQD mask to setup GFX queues for MES and KIQ
operations. We are using one queue each for KIQ operations, and
setting rest of the queues for MES scheduling.
This also fixes a r
On Tue, Oct 15, 2024 at 12:33 PM Shashank Sharma
wrote:
>
> This patch sets MES HQD mask to setup GFX queues for MES and KIQ
> operations. We are using one queue each for KIQ operations, and
> setting rest of the queues for MES scheduling.
>
> This also fixes a regression for missing Navi 4x MES m
On 15/10/2024 16:58, Alex Deucher wrote:
On Tue, Oct 15, 2024 at 6:13 AM Sharma, Shashank
wrote:
Hello Alex,
On 14/10/2024 22:29, Deucher, Alexander wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Sharma, Shashank
Sent: Thursday, October 10
This patch sets MES HQD mask to setup GFX queues for MES and KIQ
operations. We are using one queue each for KIQ operations, and
setting rest of the queues for MES scheduling.
This also fixes a regression for missing Navi 4x MES mask from
usermode queue series.
V2: Rebase on staging, accommodate
On Tue, Oct 15, 2024 at 6:13 AM Sharma, Shashank
wrote:
>
> Hello Alex,
>
> On 14/10/2024 22:29, Deucher, Alexander wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> -Original Message-
> From: Sharma, Shashank
> Sent: Thursday, October 10, 2024 2:08 PM
> To: amd-gfx@
On Fri, Oct 11, 2024 at 1:33 PM Mario Limonciello
wrote:
>
> If a BIOS provides bad data in response to an ATIF method call
> this causes a NULL pointer dereference in the caller.
>
> ```
> ? show_regs (arch/x86/kernel/dumpstack.c:478 (discriminator 1))
> ? __die (arch/x86/kernel/dumpstack.c:423 a
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eD
On 10/15/2024 03:17, Wayne Lin wrote:
From: Aurabindo Pillai
[Why&How]
vblank immediate disable currently does not work for all asics. On
DCN401, the vblank interrupts never stop coming, and hence we never
get a chance to trigger idle optimizations.
Add a workaround to enable immediate disable
Hello Alex,
On 14/10/2024 22:29, Deucher, Alexander wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Sharma, Shashank
Sent: Thursday, October 10, 2024 2:08 PM
To:amd-gfx@lists.freedesktop.org
Cc: Somalapuram, Amaranath; Deucher,
Alexander; Koenig
From: Aric Cyr
This version brings along following fixes:
- Fix dcn401 idle optimization problem
- Fix cursor corruption on dcn35
- Fix DP LL compliance failures
- Fix SubVP Phantom VBlank End calculation
Acked-by: Tom Chung
Signed-off-by: Aric Cyr
Signed-off-by: Wayne Lin
---
drivers/gpu/dr
From: Bhuvanachandra Pinninti
[why & How]
The original guard is wrongly to be set as for dcn30.
Changed it from 30 to 301.
Reviewed-by: Dillon Varone
Signed-off-by: Bhuvanachandra Pinninti
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h | 4 ++--
1 file
From: Samson Tam
[Why]
Current fullscreen check in SPL using dm_helpers is out-of-sync
with dc state. This causes an issue during minimal transition
where we pick an invalid intermediate state because the pre and
post fullscreen status are different.
[How]
Add sharpening_required flag to dc_stre
From: Fangzhi Zuo
Fix DP compliance failures 4.2.2.12, 4.3.1.21, 4.9.1.19
caused by imprecise delay on fsleep().
Reviewed-by: Aric Cyr
Signed-off-by: Fangzhi Zuo
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c| 2 +-
1 file changed, 1 insertion(+
From: Dillon Varone
[WHY]
The phantom stream timing is copied from the main stream as most
parameters are identical, however some need to be recalculated.
Currently VBlank End is not recalculated and copied from the main
incorrectly.
[HOW]
Recalculate VBlank End for phantom stream timing.
Revie
From: Aurabindo Pillai
[Why&How]
Disabling P-State support on full updates for DCN401 results in
introducing additional communication with SMU. A UCLK hard min message
to SMU takes 4 seconds to go through, which was due to DCN not allowing
pstate switch, which was caused by incorrect value for TT
From: Leo Chen
[Why & How]
Array indices out of bound caused memory corruption. Adding checks to
ensure that array index stays in bound.
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Leo Chen
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/d
From: Aurabindo Pillai
Reuse subvp enable check from DCN32 for IGT testing of Sub-Viewport
feature on DCN401
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 3 ++-
1 file changed, 2 in
From: Yihan Zhu
[WHY & HOW]
Cursor corruption observed on USBC display with specific system setup with a
reboot. Cursor memory might still in the lightsleep state due to voltage
issue, we need program DISPCLK_R_GATE_DISABLE to avoid this issue only on
DCN35.
Reviewed-by: Nicholas Kazlauskas
Sig
From: Aurabindo Pillai
[Why&How]
vblank immediate disable currently does not work for all asics. On
DCN401, the vblank interrupts never stop coming, and hence we never
get a chance to trigger idle optimizations.
Add a workaround to enable immediate disable only on APUs for now. This
adds a 2-fra
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix dcn401 idle optimization problem
- Fix cursor corruption on dcn35
- Fix DP LL compliance failures
- Fix SubVP Phantom VBlank End calculation
Cc: Daniel Wheeler
---
Aric Cyr (1):
drm/amd/display: 3.2.306
Aura
On 14 October 2024 at 3:11pm, Christian Zigotzky wrote:
>> On 14 October 2024 at 3:00pm, Alex Deucher
wrote:
>>
>> Can whoever wrote this send it out as a proper patch?
>>
>> Alex
>>
> Patch source:
https://lists.freedesktop.org/archives/dri-devel/2024-October/473314.html
+ ville.syrjala
> Is this on a mainline 6.11.y or 6.12-rc3 kernel? Can you please open up a
> new issue with all the details? You can ping it back here.
Currently a Debian 6.11.2 kernel, but I did reproduce it with a
mainline 6.10 and earlier versions in the past.
Issue link: https://gitlab.freedesktop.org/dr
On 14 October 2024 at 3:00pm, Alex Deucher wrote:
Can whoever wrote this send it out as a proper patch?
Alex
Patch source:
https://lists.freedesktop.org/archives/dri-devel/2024-October/473314.html
Drop AMDGPU_USERQ_BO_WRITE as this should not be a global option
of the IOCTL, It should be option per buffer. Hence adding separate
array for read and write BO handles.
Signed-off-by: Arunpravin Paneer Selvam
Acked-by: Christian König
Suggested-by: Marek Olšák
Suggested-by: Christian König
--
Add a vm root BO lock before accessing the userqueue VM.
v1:(Christian)
- Keep the VM locked until you are done with the mapping.
- Grab a temporary BO reference, drop the VM lock and acquire the BO.
When you are done with everything just drop the BO lock and
then the temporary BO
Add the missing error handling for xa_store() call in the function
amdgpu_userq_fence_driver_alloc().
Signed-off-by: Arunpravin Paneer Selvam
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
Few optimization and fixes for userq fence driver.
v1:(Christian):
- Remove unnecessary comments.
- In drm_exec_init call give num_bo_handles as last parameter it would
making allocation of the array more efficient
- Handle return value of __xa_store() and improve the error handling of
Remove MES self test as this conflicts the userqueue fence
interrupts.
v2:(Christian)
- remove the amdgpu_mes_self_test() function and any now unused code.
Signed-off-by: Arunpravin Paneer Selvam
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 -
drivers/gpu/dr
This patch introduces new IOCTL for userqueue secure semaphore.
The signal IOCTL called from userspace application creates a drm
syncobj and array of bo GEM handles and passed in as parameter to
the driver to install the fence into it.
The wait IOCTL gets an array of drm syncobjs, finds the fence
Add support to handle the userqueue protected fence signal hardware
interrupt.
Create a xarray which maps the doorbell index to the fence driver address.
This would help to retrieve the fence driver information when an userq fence
interrupt is triggered. Firmware sends the doorbell offset value an
Screen freeze and userq fence driver crash while playing Xonotic
v2: (Christian)
- There is change that fence might signal in between testing
and grabbing the lock. Hence we can move the lock above the
if..else check and use the dma_fence_is_signaled_locked().
Signed-off-by: Arunp
Add user fence wait IOCTL timeline syncobj support.
v2:(Christian)
- handle dma_fence_wait() return value.
- shorten the variable name syncobj_timeline_points a bit.
- move num_points up to avoid padding issues.
v3:(Christian)
- Handle timeline drm_syncobj_find_fence() call error
hand
On 10/15/2024 1:08 AM, Deucher, Alexander wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
>> -Original Message-
>> From: Zhu, Jiadong
>> Sent: Wednesday, October 9, 2024 5:23 AM
>> To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander
>> Subject
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