If buddy manager have more than one roots and each root have sub-block
need to be free. When drm_buddy_fini called, the first loop of
force_merge will merge and free all of the sub block of first root,
which offset is 0x0 and size is biggest(more than have of the mm size).
In subsequent force_merge
On 8/7/2024 2:58 AM, Alex Deucher wrote:
> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri wrote:
>>
>> Add support of vcn ip dump in the devcoredump
>> for vcn_v4_0_3.
>>
>> Signed-off-by: Sunil Khatri
>> ---
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++-
>> 1 file ch
Hi
Am 07.08.24 um 21:47 schrieb Alex Deucher:
On Tue, Aug 6, 2024 at 3:06 AM Thomas Zimmermann wrote:
Hi
Am 05.08.24 um 21:00 schrieb Deucher, Alexander:
[Public]
-Original Message-
From: Thomas Zimmermann
Sent: Wednesday, July 31, 2024 8:17 AM
To: maarten.lankho...@linux.intel.co
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Kenneth Feng
Sent: Thursday, August 8, 2024 12:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Feng, Kenneth
Subject: [PAT
add HDP_SD support on gc 12.0.0/1
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/amdgpu/soc24.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c
b/drivers/gpu/drm/amd/amdgpu/soc24.c
index 7d641d0dadba..b0c3678cfb31 100644
--- a/drivers/gpu/drm/amd/am
On 8/8/2024 2:04 AM, Jonathan Kim wrote:
> When users dynamically set the partition mode through sysfs writes,
> this can lead to a double lock situation where the KFD is trying to take
> the partition lock when updating the recommended SDMA engines.
> Have the KFD do a lockless query instead to
on MI300/MI308 UBB products, when doing mode1 reset, since 1 gpu need to
wait all 8 gpus finish mode1 reset and then do re-init. As observed,
sometimes the gpu which triggered the reset need to wait 15s for all
gpus to finish.
If poll msg timeout, guest driver will send the reset message again, an
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Xiao, Jack
Sent: Wednesday, August 7, 2024 17:39
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Cc: Xiao, Jack
Subject: [PATCH 0/8] enable mes pi
Apply IH Ptr mask immediately after updating to IH Read ptr.
Ideally the operation to update and mask should be atomic. This
will ensure that Read Ptr points to a valid index in the IH
ring buffer.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 5 -
drivers/gpu/
AMDGPU_CS_NO_IMPLICIT_SYNC.
Probably wildly out of date because amd-staging-drm-next
didn't boot for me.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/
Per submission flag because:
1) Slightly simpler & more flexible than per context flag.
2) We'd need to extend the per-BO struct if we want to put
it there.
3) Doing it per BO is annoying implementation wise as we
disassociate it from the BO list before doing the fences.
4) I don't really an
Had no validation before. libdrm_amdgpu memsets this, even
for the raw/raw2 functions.
We have a lot of functions touching the ioctl struct, no
strong opinion on where this is placed, but I thought
early would be good.
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h | 1 +
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
i
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 +++
drivers/gpu/drm/amd/amdgpu
Should be safe to do. Writers of BOOKKEEP fences:
- amdgpu_vm_tlb_flush: Per the comments, only to prevent frees.
- amdgpu_vm_sdma_commit: Uses AMDGPU_FENCE_OWNER_VM, which was
already ignored by amdgpu_sync_test_fence for cs submissions.
- amdgpu_amdkfd_remove_eviction_fence: Adds a stub fen
For the rationale see the earlier RFC by Faith:
https://lists.freedesktop.org/archives/amd-gfx/2024-August/112273.html
This mainly makes two changes:
1. Uses a submission flag rather than a context creation flag.
2. Uses DMA_RESV_USAGE_BOOKKEEP to avoid adding implicit fences still.
Note that t
This partially reverts commit b7a1a0ef12b81957584fef7b61e2d5ec049c7209.
A user reported stuttering under heavy gfx load with this commit.
I suspect it's due to the fact that the gfx contexts are shared
between the pipes so if there is alot of load on one pipe, we could
end up stalling waiting for
When users dynamically set the partition mode through sysfs writes,
this can lead to a double lock situation where the KFD is trying to take
the partition lock when updating the recommended SDMA engines.
Have the KFD do a lockless query instead to avoid this.
This should work since the KFD always i
We can parse edid caps from drm_edid and drm_eld and any calls of
dm_helpers_parse_edid_caps is made in a state that we have drm_edid set
to amdgpu connector.
v5: also remove the parameter from kernel-doc (kernel test bot)
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_
drm_edid_connector_update() updates display info, filling ELD with
speaker allocation data in the last step of update_dislay_info(). Our
goal is stopping using raw edid, so we can extract SADB from drm_eld
instead of access raw edid to get audio caps.
v5: add more informative commit description (A
drm_edid_connector_update() updates display info, filling ELD with audio
info from Short-Audio Descriptors in the last step of
update_dislay_info(). Our goal is stopping using raw edid, so we can
extract SAD from drm_eld instead of access raw edid to get audio caps.
v5:
- squash with `don't give i
We don't need to parse dc_edid to get the display name since it's
already set in drm_eld which in turn had it values updated when updating
connector with the opaque drm_edid.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 10 ++
1 file changed, 6
Since [1], we can use drm_edid_product_id to get debug info from
drm_edid instead of directly parsing EDID.
[1]
https://lore.kernel.org/dri-devel/cover.1712655867.git.jani.nik...@intel.com/
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 37 ++-
1
When updating connector under drm_edid infrastructure, many calculations
and validations are already done and become redundant inside AMD driver.
Remove those driver-specific code in favor of the DRM common code.
v5:
- squash with unused variabels cleanup (Alex H.)
Signed-off-by: Melissa Wen
---
Update connector caps with drm_edid data before parsing info for
freesync.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm
Connectors have source physical address available in display
info. Use drm_dp_cec_attach() to use it instead of parsing the EDID
again.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drive
Replace raw edid handling (struct edid) with the opaque EDID type
(struct drm_edid) on amdgpu_dm_connector for consistency. It may also
prevent mismatch of approaches in different parts of the driver code.
Working in progress. It was only exercised with IGT tests.
v2: use const to fix warnings (Al
On Wed, Aug 7, 2024 at 10:25 PM Faith Ekstrand wrote:
> On Wed, Aug 7, 2024 at 2:23 PM Joshua Ashton wrote:
>
>> I was thinking about this more recently. I was initially considering
>> "maybe this should be a per-BO import," but I couldn't think of anything in
>> the GL model that would actually
Hi,
Here AMD display driver migrates from open struct edid to opaque
drm_edid. This version works on top of amd/drm-next branch since
amd-staging-drm-next doesn't have the commits that support
drm_edid_product_id[1]. It's mostly addressing Alex Hung's feedback
from the previous version.
Patches 1
On Wed, Aug 7, 2024 at 2:23 PM Joshua Ashton wrote:
> I was thinking about this more recently. I was initially considering
> "maybe this should be a per-BO import," but I couldn't think of anything in
> the GL model that would actually benefit given its not "true" bindless and
> there's no update
On Tue, Aug 6, 2024 at 3:06 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 05.08.24 um 21:00 schrieb Deucher, Alexander:
> > [Public]
> >
> >> -Original Message-
> >> From: Thomas Zimmermann
> >> Sent: Wednesday, July 31, 2024 8:17 AM
> >> To: maarten.lankho...@linux.intel.com; mrip...@kernel.
I was thinking about this more recently. I was initially considering "maybe
this should be a per-BO import," but I couldn't think of anything in the GL
model that would actually benefit given its not "true" bindless and there's no
update-after-bind there.
Worth others more familiar with GL aski
On Wed, Aug 7, 2024 at 5:39 AM Jack Xiao wrote:
>
> Use mes pipe to unmap kcq and kgq.
>
> Signed-off-by: Jack Xiao
Series is:
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 22
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 27 +
On Wed, Aug 7, 2024 at 4:21 AM Tvrtko Ursulin wrote:
>
>
> On 04/08/2024 19:11, Marek Olšák wrote:
> > On Thu, Aug 1, 2024 at 2:55 PM Marek Olšák wrote:
> >>
> >> On Thu, Aug 1, 2024, 03:37 Christian König
> >> wrote:
> >>>
> >>> Am 01.08.24 um 08:53 schrieb Marek Olšák:
> >>>
> >>> On Thu, Aug
Previously, AMDGPU_GEM_CREATE_EXPLICIT_SYNC was used to disable implicit
synchronization on BOs when explicit synchronization can be used. The
problem is that this flag is per-BO and affects all amdgpu users in the
system, not just the usermode drver which sets it. This can lead to
some unintende
Yeah, I also found that one. Will send it out this evening if you don't get
to it.
On Wed, Aug 7, 2024, 5:03 PM Michel Dänzer
wrote:
> On 2024-08-06 22:27, Bas Nieuwenhuizen wrote:
> > Missing validation ...
> >
> > Checked libdrm and it clears all the structs, so we should be
> > safe to just c
On 2024-08-06 22:27, Bas Nieuwenhuizen wrote:
> Missing validation ...
>
> Checked libdrm and it clears all the structs, so we should be
> safe to just check everything.
Thanks for fixing this.
FWIW, amdgpu_cs_ioctl has the same issue AFAICT. Haven't checked any others,
there might be more.
-
On 2024-08-07 01:13, Mario Limonciello wrote:
On 8/6/24 13:42, Sebastian Wick wrote:
From: Sebastian Wick
This reverts commit 63d0b87213a0ba241b3fcfba3fe7b0aed0cd1cc5.
The panel_power_savings sysfs entry can be used to change the displayed
colorimetry which breaks color managed setups.
Th
On Wed, Aug 7, 2024 at 6:26 AM Jack Xiao wrote:
>
> Set sched_hw_submission=8 for mes maximum packet execution.
>
> v2. Only set sched_hw_submission.
>
> Signed-off-by: Jack Xiao
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 ++
> 1 file changed, 2 insertions(
Change condition, if (ptr == NULL) to if (!ptr)
for a better format and fix the warning.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/v
*** BLURB HERE ***
Sunil Khatri (5):
drm/amdgpu: fix ptr check warning in gfx9 ip_dump
drm/amdgpu: fix ptr check warning in gfx10 ip_dump
drm/amdgpu: fix ptr check warning in gfx11 ip_dump
drm/amdgpu: fix ptr check warning in gfx12 ip_dump
drm/amdgpu: fix ptr check warning in vcn_v3 ip_d
Change if (ptr == NULL) to if (!ptr) for a better
format and fix the warning.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0
Change condition, if (ptr == NULL) to if (!ptr)
for a better format and fix the warning.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/
Change condition, if (ptr == NULL) to if (!ptr)
for a better format and fix the warning.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/
Change condition, if (ptr == NULL) to if (!ptr)
for a better format and fix the warning.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/
Set sched_hw_submission=8 for mes maximum packet execution.
v2. Only set sched_hw_submission.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu
[Public]
The maximum sched_hw_submission value will be set to 8. The value will result
that the maximum number of packet execution which is not greater than firmware
allowed.
Regards,
Jack
-Original Message-
From: Deucher, Alexander
Sent: Tuesday, August 6, 2024 10:34 PM
To: Xiao, Jac
Use mes pipe to unmap kcq and kgq.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 22
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 27 +
2 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/a
Configure tow pipes with different hardware resources.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 77 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 12 ++--
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 7 +--
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
Add mes pipe switch to let caller choose pipe
to submit packet.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 59 ++
1 file changed, 33 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgp
Free memory for two pipes and unmap pipe0 via pipe1.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 31 +-
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0
Adjust mes12 sw/hw initiailization for both pipe0 and pipe1
enablement. The two pipes are almost identical pipe. Pipe0
behaves like schq and pipe1 like kiq, pipe0 was mapped by pipe1.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 106 +++--
1 file chan
Enable unified mes firmware to load on pipe0 and pipe1.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 27 +++--
2 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
Enable both pipe0 and pipe1 running unified mes firmware.
They are almost identical pipe, but pipe1 behaves more like legacy kiq.
As per fw design, pipe0 is required to be mapped by pipe1 to make
some fw feature work.
Jack Xiao (8):
drm/amdgpu/mes12: update mes_v12_api_def.h
drm/amdgpu/mes: ad
Add multiple mes ring instances in mes structure to support
multiple mes pipes.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 4 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu
Update mes12 api definition.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/include/mes_v12_api_def.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
index ffd67c6ed9b3..302
The function is unused. Remove it.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_fb_helper.c | 15 ---
include/drm/drm_fb_helper.h | 6 --
2 files changed, 21 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index f6667d
The output_poll_changed hook was only necessary before in-kernel
DRM clients existed, but is now obsolete. The client code handles
display otplugging internally.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 1 -
drivers/gpu/drm/nouveau/nouveau_display.c | 1 -
The output_poll_changed hook in struct drm_mode_config_funcs is
unused. Remove it. The helper drm_client_dev_hotplug() implements
the callback's functionality.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_probe_helper.c | 10 +-
include/drm/drm_mode_config.h | 16 ---
Replace the callto drm_fb_helper_output_poll_changed() with a call
to drm_client_dev_hotplug(). It's equivalent in functionality, but
use the DRM client infrastructure.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/nouveau/nouveau_vga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
The lastclose callback in struct drm_driver is unused. Remove it. Also
inline the now trivial drm_lastclose() and update documentation.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_drv.c | 5 ++---
drivers/gpu/drm/drm_fb_helper.c | 18 +
drivers/gpu/drm/drm_fil
After switching all drivers' fbdev emulation to DRM client, the
old fbdev hooks are now obsolete. Only amgdpu and nouveau still use
them in a several places. Remove the hooks from the drivers and the
DRM core.
The series would ideally be merged at once via drm-misc-next.
Thomas Zimmermann (8):
Remove the implementation of struct drm_driver.lastclose. The hook
was only necessary before in-kernel DRM clients existed, but is now
obsolete.
The code within amdgpu_driver_lastclose_kms() is performed elsewhere
in the DRM fbdev emulation.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/
Remove the implementation of struct drm_driver.lastclose. The hook
was only necessary before in-kernel DRM clients existed, but is now
obsolete.
The code within nouveau_vga_lastclose() is performed elsewhere in the
DRM fbdev emulation.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/nouvea
Amdgpu and nouveau call vga_switcheroo_process_delayed_switch() from
their lastclose callbacks. Call it from the fbdev lastclose helper,
so that the driver functions can finally be removed.
The fbdev call is part of all lastclose handling that restores the
DRM fbcon terminal. Only PCI devices with
Ptrace access VRAM bo will first try sdma access in
amdgpu_ttm_access_memory_sdma(), if fails, it will fallback to mmio
access.
Since ptrace only access 8 bytes at a time and
amdgpu_ttm_access_memory_sdma() only allow PAGE_SIZE bytes access,
it returns fail.
On SRIOV, mmio access will also fail as
On 04/08/2024 19:11, Marek Olšák wrote:
On Thu, Aug 1, 2024 at 2:55 PM Marek Olšák wrote:
On Thu, Aug 1, 2024, 03:37 Christian König wrote:
Am 01.08.24 um 08:53 schrieb Marek Olšák:
On Thu, Aug 1, 2024, 00:28 Khatri, Sunil wrote:
On 8/1/2024 8:49 AM, Marek Olšák wrote:
+ /* He
Reviewed-by: Tom Chung
On 8/7/2024 9:20 AM, Srinivasan Shanmugam wrote:
This commit adds a null check for the 'afb' variable in the
amdgpu_dm_update_cursor function. Previously, 'afb' was assumed to be
null at line 8388, but was used later in the code without a null check.
This could potentiall
Reviewed-by: Tom Chung
On 8/7/2024 9:20 AM, Srinivasan Shanmugam wrote:
This commit adds a null check for the 'afb' variable in the
amdgpu_dm_plane_handle_cursor_update function. Previously, 'afb' was
assumed to be null, but was used later in the code without a null check.
This could potentiall
From: Martin Leung
This version brings along following fixes:
- Fix some cursor issue
- Fix print format specifiers in DC_LOG_IPS
- Fix minor coding errors in dml21 phase 5
- Improve FAM control for DCN401
- Add null pointer checks for some code
- Refactor 3DLUT for non-DMA
- Optimize vstartup po
From: Rodrigo Siqueira
[why & how]
Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, since
those macros are not necessary anymore at the dpp1 set degamma. Those
are part of an old implementation.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
From: Melissa Wen
[why & how]
Cursor gets clipped off in the middle of the screen with hw
rotation 180. Fix a miscalculation of cursor offset when it's
placed near the edges in the pipe split case.
Cursor bugs with hw rotation were reported on AMD issue
tracker:
https://gitlab.freedesktop.org/dr
From: Rodrigo Siqueira
[why & how]
When the commit 9d84c7ef8a87 ("drm/amd/display: Correct cursor position
on horizontal mirror") was introduced, it used the wrong calculation for
the position copy for X. This commit uses the correct calculation for that
based on the original patch.
Fixes: 9d84c
From: Rodrigo Siqueira
[why & how]
When the commit 32caf32d5b06 ("drm/amd/display: Add driver support for
future FAMS versions") was introduced, it missed some of the FAM2 code.
This commit introduces the code that control the FAM enable and disable.
Fixes: 32caf32d5b06 ("drm/amd/display: Add dr
From: Rodrigo Siqueira
[why & how]
Remove force_backlight_start_level since it is never used.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/
From: Charlene Liu
[why & how]
this is to remove redundant msg to pmfw at boot/resume
since bios already power up dcn.
Reviewed-by: Chris Park
Signed-off-by: Charlene Liu
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 7 +--
1 file changed, 5 ins
From: Loan Chen
[Why]
Tiled display cannot synchronize properly after S3.
The fix for commit 5f0c74915815 ("drm/amd/display: Fix for otg
synchronization logic") is not enable in DCN321, which causes
the otg is excluded from synchronization.
[How]
Enable otg synchronization logic in dcn321.
Fixe
From: Dillon Varone
[WHY&HOW]
Set max VTotal cap for dcn401 because VTotal
register is only 16 bits wide on dcn401.
Reviewed-by: Chris Park
Signed-off-by: Dillon Varone
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file changed, 1 inse
From: Dillon Varone
[WHY]
In certain scenarios DC can internally trigger back to back full updates
which will miss some required programming that is normally deferred
until post update via optimize_bandwidth.
[HOW]
In back to back update scenarios, wait for pending updates to complete
and perfor
From: Dillon Varone
[WHY&HOW]
It is not guaranteed even for HW exclusive P-State methods (like
VActive) that P-state will be supported properly until optimize
bandwidth is called, so unconditionally disable it on full updates.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by:
From: Dillon Varone
[WHY]
Stream ID's associated with phantom pipes can change often as they
are reconstructed on full updates, however they can remain identical
depending on the required update.
[HOW]
In the case phantom streams and pipe topologies remain the same
between updates, mark the tran
From: Robin Chen
[Why]
In current design, the vstartup position is adjusted to
vblank start position when AS-SDP is enabled.
However when the vblank length is too big, it may over
vstartup boundary.
[How]
To adjust vstartup position to 1 line before vsync position.
Reviewed-by: Anthony Koo
Sig
From: Roman Li
[Why]
%d specifier is used for printing unsigned values.
It can result in negative values in logs for unsigned variables.
[How]
Replace %d with %u for unsigned.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Roman Li
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/d
From: Wayne Lin
[why & how]
Make sure plane_state is not null before calling a function
that dereferences it. Besides, remove redundant codes.
Reviewed-by: Alex Hung
Signed-off-by: Wayne Lin
Signed-off-by: Tom Chung
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 22 +++
From: Rodrigo Siqueira
[why & how]
Change the order of the pipe_ctx->plane_state check to ensure that
plane_state is not null before accessing it.
Reviewed-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 11 ++
From: Muhammad Ahmed
[why & how]
HW removed this w/a, but we will still keep it to avoid regression.
but return in test mode.
Reviewed-by: Charlene Liu
Signed-off-by: Muhammad Ahmed
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 3 +++
1 file chan
From: Aurabindo Pillai
[why & how]
print additional info for MALL related calculations and DMCUB messaging
to aid debugging.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 10 --
driv
From: Austin Zheng
[Why]
DML21 does not allocate DET evenly between pipes.
May result in underflow when unlocking the pipes as DET could
be overallocated.
[How]
1. Unlock pipes that have a decreased amount of DET allocation
2. Wait for the double buffer to be updated.
3. Unlock the remaining pip
From: Alex Hung
[WHY & HOW]
dc->clk_mgr is null checked previously in the same function, indicating
it might be null.
Passing "dc" to "dc->hwss.apply_idle_power_optimizations", which
dereferences null "dc->clk_mgr". (The function pointer resolves to
"dcn35_apply_idle_power_optimizations".)
This
From: Hansen Dsouza
[Why and how]
Update to using new dccg callbacks
Reviewed-by: Chris Park
Signed-off-by: Hansen Dsouza
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
From: Relja Vojvodic
[Why]
Currently the handling for 3DLUT is found in multiple different
places, which causes issues when the different functions are not
in sync with each other.
Frequently bugs occur because the LUT handling is broken up, and
what has already been handled isn't kept track of w
From: Wenjing Liu
[why]
Based on power measurement result, in most cases when display clock
is higher than Vmin display clock, lowering display clock using
dynamic ODM will improve overall power consumption by 0 to 4 watts
even if we can't reach Vmin.
[how]
Allow vmin optimization applied even i
From: Wenjing Liu
[why & how]
There is a coding error which causes incorrect variables to be assigned
in DML21 phase 5.
Reviewed-by: Austin Zheng
Signed-off-by: Wenjing Liu
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c | 4 ++--
1 file changed, 2
- Fix some cursor issue
- Fix print format specifiers in DC_LOG_IPS
- Fix minor coding errors in dml21 phase 5
- Improve FAM control for DCN401
- Add null pointer checks for some code
- Refactor 3DLUT for non-DMA
- Optimize vstartup position for AS-SDP
- Update to using new dccg callbacks
- Enable
Several cs track offsets (such as 'track->db_s_read_offset')
either are initialized with or plainly take big enough values that,
once shifted 8 bits left, may be hit with integer overflow if the
resulting values end up going over u32 limit.
Same goes for a few instances of 'surf.layer_size * mslic
Hi,
>
> Hi Yamato-san,
>
>
> On 2024-08-06 04:43, Masatake YAMATO wrote:
>> Though drmCommandWriteRead() is used in libdrm [1],
>> DRM_IOCTL_AMDGPU_GEM_VA uses DRM_IOW for encoding.
>>
>> [1]
>> https://gitlab.freedesktop.org/mesa/drm/-/blob/main/amdgpu/amdgpu_bo.c?ref_type=heads
>
> AFAICT
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