On Fri, May 31, 2024 at 1:57 AM Andy Shevchenko <
andriy.shevche...@linux.intel.com> wrote:
> On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote:
> > We can skip children resources when the parent resource does not cover
> > the range.
> >
> > This should help vmf_insert_* users on x86, suc
On 2024-05-30 21:44, Zhang, Jesse(Jie) wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Felix,
-Original Message-
From: Kuehling, Felix
Sent: Friday, May 31, 2024 4:37 AM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christia
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 0e1980c40b6edfa68b6acf926bab22448a6e40c9 Add linux-next specific
files for 20240531
Unverified Error/Warning (likely false positive, please contact us if
interested):
drivers/gpu/drm/xe
On 2024-05-30 22:51, Jesse Zhang wrote:
To fix the warning about unused value,
remove the use_static and use the parameter is_static directly.
Signed-off-by: Jesse Zhang
Suggested-by: Felix Kuehling
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c |
On 2024-05-30 22:51, Jesse Zhang wrote:
The expression caps | HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED
and caps | HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED
are always 1/true regardless of the values of its operand.
Fixes: 75de8428c3d632 ("drm/amdkfd: enable single alu op
Applied. Thanks!
On Fri, May 31, 2024 at 12:31 PM Tasos Sahanidis wrote:
>
> Flexible arrays used [1] instead of []. Replace the former with the latter
> to resolve multiple UBSAN warnings observed on boot with a BONAIRE card.
>
> In addition, use the __counted_by attribute where possible to hin
Applied. Thanks!
Alex
On Fri, May 31, 2024 at 11:37 AM Randy Dunlap wrote:
>
>
>
> On 5/31/24 2:32 AM, Colin Ian King wrote:
> > There are a few spelling mistakes in dml2_printf messages. Fix them.
> >
> > Signed-off-by: Colin Ian King
>
>
> Reviewed-by: Randy Dunlap
>
> Thanks.
>
> > ---
> >
This reverts commit 269226a8fdf2cac0e03920f9ba0d670a056af3d6.
Pierre-Eric reported problems with this on his navi33. Revert
for now until we understand what is going wrong.
Signed-off-by: Alex Deucher
Cc: pierre-eric.pelloux-pra...@amd.com
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++---
From: Dillon Varone
- Ensure SubVP stream settings match ODM policy
- Fix MALL size calculations when DCC is enabled
- Fail if any stream fails DRR policy check
Reviewed-by: Chaitanya Dhere
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
.../amd/display/dc/dml2/dml21/dml21_utils.c
From: Wayne Lin
[Why]
enc10->base.features.flags.bits.DP_IS_USB_C will be overwritten if we set it
before initializing enc10->base.features
[How]
Determine DP_IS_USB_C after enc10->base.features is initialized. Besides,
bp_cap_info.DP_IS_USB_C will never be set in get_connector_speed_cap_info().
From: Chiawen Huang
[How&Why]
Once IPS active, all the DCN resources are
not be allowed to access.
It needs to a function for 3rd party to
on/off IPS.
Reviewed-by: Duncan Ma
Acked-by: Zaeem Mohamed
Signed-off-by: Chiawen Huang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++
dri
From: Alvin Lee
[Description]
In newer DCN's the programming of SYMCLK_FE_SRC_SEL depends on
the value of DIG_FE_SOURCE_SELECT. If DIG_FE_SOURCE_SELECT is not
already programmed at the time of PHY / DIG enable then the FW
sequence will program an incorrect SYMCLK source. Ensure that we
program DI
From: Fangzhi Zuo
IPX involvment proven to affect LT, causing link loss. Need to prevent
IPX enabled in LT process in which link detect and set mode are main
procedures that have LT taken place.
Reviewed-by: Roman Li
Acked-by: Zaeem Mohamed
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/
From: Dillon Varone
[WHY&HOW]
UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update
to SMU. When this happens, the UCLK provided should be max if switching is
unsupported.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
.../dc/clk_m
From: Daniel Sa
[Why]
When performing P-State switching with Subvp on 8k (downscaled to 4k).
corruption can be seen on the screen. MALL data was not being fetched
from DC, and the system things there is more MALL space then what is
actually available.
[How]
Read MALL size from dc caps.
Reviewed
From: Aric Cyr
This version brings the following changes:
- Add sequential ONO sequencing for DCN35
- Add new GPINT command definitions
- reduce ODM slice count to initial new dc state only when needed
- Enable copying of bounding box data from VBIOS DMUB
- Guard reading 3DLUT registers for dcn32
From: Dillon Varone
[WHY&HOW]
Improves on the SMU interface to explicitly declare P-State support.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 133 --
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h
From: Jack Chang
1. To support multiple PSRSU residency measurement mode
Reviewed-by: Wenjing Liu
Acked-by: Zaeem Mohamed
Signed-off-by: Jack Chang
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c| 2 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c| 5 -
drivers/gpu/d
From: Alex Hung
Two additional virtual links are created and thus increasing size
for dc->links by two.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
From: Nicholas Kazlauskas
[Why]
3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers
now exist in MCM state.
[How]
Add guards when reading DPP state based on whether the register has a
valid offset.
Reviewed-by: Sung joon Kim
Acked-by: Zaeem Mohamed
Signed-off-by: Nicholas Kaz
From: Alvin Lee
[Description]
Refactor code and move fpo_in_use into stream_status to avoid
unexpected changes to previous dc_state (i.e., current_state).
Since stream pointers are shared between current and new dc_states,
updating parameters of one stream will update the other as well
which caus
From: Nicholas Susanto
[Why]
When an eDP with high clock states is going into s0i3, stream_count is
0. This causes DML to not update the clks to the lowest state and
blocking us to enter s0i3 since eDP is out of vmin.
[How]
When stream_count is 0, set all the clocks to the lowest state.
Revie
From: Dillon Varone
[WHY&HOW]
Add 5ms timeout to trigger recovery and force allow P-State in DMUB.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c| 1 +
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 +
2 f
From: ChunTao Tso
Add functions to defer updating of coasting vtotal after source refresh rate
update.
Reviewed-by: Robin Chen
Acked-by: Zaeem Mohamed
Signed-off-by: ChunTao Tso
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
.../drm/amd/display/modules/power/power_helpers.c
From: Lewis Huang
[Why]
For some panel, it cannot handle pseudo vblank set by otg resync
when leave psr
[How]
The monitor patch will keep otg_on during enter IPS1.
And then we don't need to do otg resync when wake up.
Reviewed-by: Duncan Ma
Acked-by: Zaeem Mohamed
Signed-off-by: Lewis Huang
From: Yihan Zhu
[WHY]
OPPs couldn't disconnect from the ODM that cause the double buffer pending not
being latched due to missing VUPDATE.
[HOW]
Moving memory blanking before OTG turn off to make sure double buffer latched
correctly.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Zaeem Mohamed
S
From: Sung Joon Kim
[why]
There are other factors that determine the number
of DSC slices. The slices should not be determined
in DML but retrieve the value calculated from driver.
[how]
Update the logic to determine DSC slice.
Make DSCDelay per display pipe.
Reviewed-by: Jun Lei
Acked-by: Zae
From: Samson Tam
[Why]
Missing check causes sequence error which results in chroma
filter coefficients not being updated in certain modes
when we display YUV video in fullscreen. This results in
color corruption in video
[How]
Add back chroma_coef_mode check in dscl_set_scl_filter
so that f
From: Alvin Lee
[Description]
When checking the subvp type of the previous state we must
pass in current_state to the interface instead of context
otherwise we will get the wrong result.
Reviewed-by: Samson Tam
Acked-by: Zaeem Mohamed
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/
From: Alvin Lee
[Description]
Today for MED update type we do not call update clocks. However, for FPO
the assumption is that update clocks should be called to disable P-State
switch before any HW programming since FPO in FW and driver are not
synchronized. This causes an issue where on a MED upd
From: Nicholas Kazlauskas
[Why]
HPD sense changes can occur during low power states and need to be
notified from firmware to driver. Upon notification the hotplug
redetection routines should execute.
[How]
Add Support in DMUB srv and DMUB srv stat for receiving these
notifications. DM can hook t
From: Relja Vojvodic
why:
optc_401_set_drr was using an old optc3 function to update vtotal min and max,
causing crashes when disabling FAMS2
how:
Updated dcn401 to point to opt401 function for vtotal updates. This version of
the function has FAMS2 logic that allows for FAMS2 to be disabled.
Re
From: Joshua Aberback
[Why]
Currently there's an issue on DCN401 that prevents oled eDP panels from
being lit up that is still under investigation. To unblock dev work
while investigating, we can work around the issue by skipping toggling
the enablement of the backlight.
[How]
- new debug bit t
From: Dillon Varone
[WHY&HOW]
When updating clocks via SMU, DAL needs to wait for requests to be fulfilled
before proceeding.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Dillon Varone
---
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h| 3 +-
.../clk_mgr/dcn401/dcn401_clk_
From: Joan Lee
[why & how]
Sometimes read DPCD return fail while result not retrieved yet. Add
retries mechanism in Replay handle hpd irq to get real result.
Reviewed-by: Jerry Zuo
Acked-by: Zaeem Mohamed
Signed-off-by: Joan Lee
---
.../dc/link/protocols/link_dp_irq_handler.c | 26
From: Joshua Aberback
[Why]
The values calculated in optc1_get_otg_active_size are assigned to the
wrong output parameters, vertical blank is being used for horizontal size
and vice versa. This results in DPG test pattern looking wrong during
hardware init, as the DPG dimensions get assigned from
From: Chris Park
[Why]
Page table definition increased up to 2MB.
[How]
Define new use case of page table for VA.
Reviewed-by: Alvin Lee
Acked-by: Zaeem Mohamed
Signed-off-by: Chris Park
---
.../display/dc/hubbub/dcn20/dcn20_hubbub.c| 27 ---
.../gpu/drm/amd/display/dc/i
From: Chun-LiangChang
[Why]
Add parameters for set_abm_event to enable varibright scaling.
VariBright Scaling is a feature to refer to system states like
1. Power mode
2. Battery Life percent
3. FullScreen video
4. Backlight slider
to adjust variBright strength to get low power or user experien
From: Wenjing Liu
[why]
In order to support glitchless display clock ramping for virtual stream,
we must
turn on symclk for stream encoder. The code will power on phy and enable
symclk
for dio encoder during virtual stream dpms sequence.
Reviewed-by: Dillon Varone
Acked-by: Zaeem Mohamed
Signe
This DC patchset brings improvements in multiple areas. In summary, we have:
* DML2 fixes
* FAMS2 Improvements
* Fix YUV video color corruption, oled eDP not lighting up DCN401
* add UCLK p-state support message for DCN401
* Extends PSRSU residency mode
* Introducing deferred replay coasting vtota
From: yi-lchen
[why]
Vbios & Driver have difference pixel rate div policy.
When enabling fast boot & performing blank & unblank w/o timing setting,
pixel clock & pixel rate dividor are not match.
It would cause too high pixel reate and eDP would be black screen.
[How]
We would keep pixel rate di
From: Frank Min
1. Add dcc buffer flag for copy buffer
2. Add sdma 7.0 support copy dcc buffer
Signed-off-by: Likun Gao
Signed-off-by: Frank Min
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++
From: Likun Gao
Deal with AMDGPU_GEM_CREATE_GFX12_DCC to set DCC bit
when needed.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 3 +++
2 files changed, 9 insert
From: Marek Olšák
define new gfx12 uapi flags
Signed-off-by: Marek Olšák
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index ae3f4e275f2
Add some additional registers.
Signed-off-by: Alex Deucher
---
.../include/asic_reg/gc/gc_12_0_0_offset.h| 8 ++
.../include/asic_reg/gc/gc_12_0_0_sh_mask.h | 98 +++
2 files changed, 106 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.
Add additional VM PTE bits.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index acd1b55b8b0e..a14cf93417c7 100644
--- a/drivers/gpu/drm/am
On 2024-05-31 2:52, Christian König wrote:
> Am 31.05.24 um 00:02 schrieb Felix Kuehling:
>> On 2024-05-28 13:23, Yunxiang Li wrote:
>>> These functions are missing the lock for reset domain.
>>>
>>> Signed-off-by: Yunxiang Li
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
reset cause is requested by customer as additional
info for gpu reset smi event.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 34 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 9 ++-
drivers/g
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Deucher, Alexander
Sent: Friday, May 31, 2024 10:24 PM
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking
Subject: RE: [PATCH 04/18] drm/amdgpu: refine mes firmware loading
[AMD Offic
[AMD Official Use Only - AMD Internal Distribution Only]
Hi, Christian
I think we have a discussion about this before . Alex also have a change that
allow driver to use different write back address for the fence for each
submission for the original issue .
From MES point of view , MES will u
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Wang, Yang(Kevin)
> Sent: Friday, May 31, 2024 2:53 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
>
> Subject: [PATCH 04/18] drm/amdgpu: refine mes firmware loading
>
On Fri, May 31, 2024 at 6:32 AM Lin.Cao wrote:
>
> Flag "mes.ring.shced.ready" will be set as true after mes hw init and set
> as false when mes hw fini to avoid duplicate initialization. But hw fini
> will not be called when function level reset, which will cause mes hw
> init be skipped during F
On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote:
> We can skip children resources when the parent resource does not cover
> the range.
>
> This should help vmf_insert_* users on x86, such as several DRM drivers.
> On my AMD Ryzen 5 7520C, when streaming data from cpu memory into amdgpu
>
There are a few spelling mistakes in dml2_printf messages. Fix them.
Signed-off-by: Colin Ian King
---
.../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
.../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
We have a guid_t type for GUIDs, switch to using it instead of hand
rolling buffers. Convert to guid_gen() in separate patches to pinpoint
the functional changes.
BR,
Jani.
Jani Nikula (3):
drm/mst: switch to guid_t type for GUID
drm/mst: switch to guid_gen() to generate valid GUIDs
drm/amd
On Thu, May 30, 2024 at 11:07:53AM +0300, Dmitry Baryshkov wrote:
> On Thu, 30 May 2024 at 07:41, Limonciello, Mario
> wrote:
> >
> >
> > >> Also a direct acpi_lid_open() call seems a bit iffy. But I guess if
> > >> someone needs this to work on non-ACPI system they get to figure out
> > >> how to
From: Palmer Dabbelt
I get a handful of build errors along the lines of
linux/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:58:13:
error: stack frame size (2352) exceeds limit (2048) in
'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalcu
Instead of just smashing jiffies into a GUID, use guid_gen() to generate
RFC 4122 compliant GUIDs.
Signed-off-by: Jani Nikula
---
Side note, it baffles me why amdgpu has a copy of this instead of
plumbing it into drm mst code.
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++--
Instead of just smashing jiffies into a GUID, use guid_gen() to generate
RFC 4122 compliant GUIDs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topolog
The kernel has a guid_t type for GUIDs. Switch to using it, but avoid
any functional changes here.
Signed-off-by: Jani Nikula
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 67 +++
include/drm/display/drm_dp_mst_helper.h
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Friday, May 31, 2024 6:04 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Koenig, Christ
Skip scheduling coredump when gpu reset is intentionally triggered
through debugfs.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
i
PMFW needs the flag to know the reason of mode1.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 2 +-
drivers/gpu
Set the flag to true if bad page number reaches threshold.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 ++
drivers/gpu/drm/amd/amdgpu/am
Check it in mode1 reset.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 32 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 1 +
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 2 +-
.../drm
Check RMA status in bad page retirement flow.
v2: fix coding bugs in v1.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 28 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 8 +++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c | 4 +++-
3 files changed
Reduce redundant code and user doesn't need to pay attention to RAS
details.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 13 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 14 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 31 -
Flag "mes.ring.shced.ready" will be set as true after mes hw init and set
as false when mes hw fini to avoid duplicate initialization. But hw fini
will not be called when function level reset, which will cause mes hw
init be skipped during FLR, which will leads to mapping legacy queue
fail. Set thi
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Bob Zhou
Sent: Friday, May 31, 2024 4:22 PM
To: amd-gfx@lists.freedesktop.org; Wang, Yang(Kevin) ;
Huang, Tim ; Zhang, Jesse(Jie)
Cc: Deucher, Alexander ; Koen
Am 16.05.24 um 21:21 schrieb Alex Deucher:
On Thu, May 16, 2024 at 8:18 AM Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Reduced re-spin of my previous series after Christian corrected a few
misconceptions that I had. So lets see if what remains makes sense or is still
misguided.
To summarise,
Check return value to avoid null pointer dereference.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_p
[AMD Official Use Only - AMD Internal Distribution Only]
Good catch! Thanks for your comments. I will fix this on next patch.
Regards,
Bob
-Original Message-
From: Wang, Yang(Kevin)
Sent: 2024年5月31日 15:43
To: Zhou, Bob ; amd-gfx@lists.freedesktop.org; Huang, Tim
; Zhang, Jesse(Jie)
Cc
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: amd-gfx On Behalf Of Bob Zhou
Sent: Friday, May 31, 2024 3:36 PM
To: amd-gfx@lists.freedesktop.org; Huang, Tim ; Zhang,
Jesse(Jie)
Cc: Deucher, Alexander ; Koenig, Christian
; Zhou, Bob
Subject: [PATCH]
Check return value to avoid null pointer dereference.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Bob Zhou
> Sent: Friday, May 31, 2024 3:01 PM
> To: amd-gfx@lists.freedesktop.org; Huang, Tim ; Zhang,
> Jesse(Jie)
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Zhou, Bob
> Subject: [PATCH v3] drm/amd/pm:
Check return value and conduct null pointer handling to avoid null pointer
dereference.
Signed-off-by: Bob Zhou
---
.../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 29 ---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega1
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