[Public]
Thanks for your comments.
I should clarify the issue. As you see the amdgpu_i2c_get_byte code:
if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
*val = in_buf[0];
DRM_DEBUG("val = 0x%02x\n", *val);
} else
Clear warning that uses uninitialized value fw_size.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index d9dc5485..6b8
[AMD Official Use Only - General]
Thanks for your comments.
I should clarify the issue. As you see the amdgpu_i2c_get_byte code:
if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
*val = in_buf[0];
DRM_DEBUG("val = 0x%02x\n", *val)
Am 22.04.24 um 21:59 schrieb Sonny Jiang:
From: Sonny Jiang
VCN5 session info package interface changed
Signed-off-by: Sonny Jiang
Mhm, in general we should push back on FW changes which makes stuff like
that necessary. So what is the justification?
If the FW has a good justification for
Am 22.04.24 um 16:37 schrieb Alex Deucher:
As we use wb slots more dynamically, we need to lock
access to avoid racing on allocation or free.
Wait a second. Why are we using the wb slots dynamically?
The number of slots made available is statically calculated, when this
is suddenly used dynam
Am 23.04.24 um 04:53 schrieb Ma, Jun:
unsigned int client_id, src_id;
struct amdgpu_irq_src *src;
bool handled = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 924baf58e322..f0a63d084b4d 100644
--- a/drivers/gpu
[AMD Official Use Only - General]
OK
-
Best Regards,
Thomas
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, April 23, 2024 11:27 AM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Li, Candice ; Wang,
Yang(Kevin) ; Yang, Stanley
Subject: RE: [P
Am 23.04.24 um 07:33 schrieb Bob Zhou:
Because the val isn't initialized, a random variable is set by
amdgpu_i2c_put_byte.
So fix the uninitialized issue.
Well that isn't correct. See the code here:
amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
amdgpu_c
Am 23.04.24 um 05:13 schrieb Li, Yunxiang (Teddy):
[Public]
We can't do this technically as there are cases where we skip full device reset
(even then amdgpu_in_reset will return true). The better thing to do is to move
amdgpu_device_stop_pending_resets() later in
gpu_recover()- if a device h
Am 22.04.24 um 21:45 schrieb Yunxiang Li:
Reset request from KFD is missing a check for if a reset is already in
progress, this causes a second reset to be triggered right after the
previous one finishes. Add the check to align with the other reset sources.
NAK, that isn't how this should be ha
Because the val isn't initialized, a random variable is set by
amdgpu_i2c_put_byte.
So fix the uninitialized issue.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c
b/
In amdgpu_umc_bad_page_polling_timeout, the amdgpu_umc_handle_bad_pages
will be run many times so that double free err_addr in some special case.
So set the err_addr to NULL to avoid the warnings.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 1 +
1 file changed, 1 insert
In amdgpu_umc_bad_page_polling_timeout, the amdgpu_umc_handle_bad_pages
will be run many times so that double free err_addr in some special case.
So set the err_addr to NULL to avoid the warnings.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 1 +
1 file changed, 1 insert
Add job that runs igt on top of vkms.
Acked-by: Maíra Canal
Acked-by: Helen Koike
Signed-off-by: Vignesh Raman
Acked-by: Jessica Zhang
Tested-by: Jessica Zhang
Acked-by: Maxime Ripard
Signed-off-by: Helen Koike
---
MAINTAINERS | 1 +
drivers/gpu/drm/ci/gi
With latest IGT, the tests tries to load the module and it
fails. So build the virtual GPU driver for virtio as module.
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/build.sh | 1 -
drivers/gpu/drm/ci/igt_runner.sh | 6 +++---
drivers/gpu/drm/ci/ima
zlib.net is not allowing tarball download anymore and results
in below error in kernel+rootfs_arm32 container build,
urllib.error.HTTPError: HTTP Error 403: Forbidden
urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
Uprev mesa to latest version which includes a fix for this issue.
ht
Uprev mesa and IGT to the latest version. Stop vendoring the
testlist into the kernel. Instead, use the testlist from the
IGT build to ensure we do not miss renamed or newly added tests.
Update the xfails with the latest testlist run.
Also build virtual GPU driver for virtio as module.
This series
[AMD Official Use Only - General]
Shall we move the check to the aca helper function?
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Tuesday, April 23, 2024 11:14
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ;
Zhou1, Tao ; Li, Candice ; Wang,
Yang(
Reviewed-by: Tom Chung
On 4/23/2024 9:59 AM, Srinivasan Shanmugam wrote:
This commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`
function.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177:
warning: This comment starts with '/**
Fix ras mode2 reset failure in ras aca mode for
sdma v4_4_2 and gfx v9_4_3.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
[Public]
> We can't do this technically as there are cases where we skip full device
> reset (even then amdgpu_in_reset will return true). The better thing to do is
> to move amdgpu_device_stop_pending_resets() later in
> gpu_recover()- if a device has undergone full reset, then cancel all pendi
On 4/23/2024 1:15 AM, Yunxiang Li wrote:
> Reset request from KFD is missing a check for if a reset is already in
> progress, this causes a second reset to be triggered right after the
> previous one finishes. Add the check to align with the other reset sources.
>
> Signed-off-by: Yunxiang Li
On 4/22/2024 7:25 PM, Christian König wrote:
> Am 22.04.24 um 11:49 schrieb Ma Jun:
>> Initialize the variables which were not initialized
>> to fix the coverity issue "Uninitialized scalar variable"
>
> Feel free to add my Acked-by to the first two patches, but this here
> clearly doesn't loo
During SRIOV reset, if a step fails and we retry, it locks kfd_locked
again but later only unlocks it once. This means all future attempts at
opening /dev/kfd will fail.
Fix the locking error and rework the SRIOV path to use the same reset
loop from the caller. Hopefully this makes the code easier
On 2024-04-22 16:14, Alex Deucher wrote:
On Mon, Apr 22, 2024 at 3:52 PM Yunxiang Li wrote:
Reset request from KFD is missing a check for if a reset is already in
progress, this causes a second reset to be triggered right after the
previous one finishes. Add the check to align with the other re
This commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`
function.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177:
warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.
The buffer size is determined by the declaration char fw_name[30]; This
means fw_name can hold up to 30 characters, including the null character
that marks the end of the string.
The string to be written is "amdgpu/%s_mec.bin" or "amdgpu/%s_rlc.bin",
where %s will be replaced by the value of chip_
The buffer size is determined by the declaration char fw_name[30]; This
means fw_name can hold up to 30 characters, including the null character
that marks the end of the string.
The string to be written is "amdgpu/%s_mec.bin" or "amdgpu/%s_rlc.bin",
where %s will be replaced by the value of chip_
From: Lijo Lazar
[ Upstream commit 4b18a91faf1752f9bd69a4ed3aed2c8f6e5b0528 ]
Downgrade to debug information when IBs are skipped. Also, use dev_* to
identify the device.
Signed-off-by: Lijo Lazar
Reviewed-by: Christian König
Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
Signed-off-by
From: Zhigang Luo
[ Upstream commit d06af584be5a769d124b7302b32a033e9559761d ]
If there are more than one device doing reset in parallel, the first
device will call kfd_suspend_all_processes() to evict all processes
on all devices, this call takes time to finish. other device will
start reset an
From: Lijo Lazar
[ Upstream commit f7e232de51bb1b45646e5b7dc4ebcf13510f2630 ]
VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In
certain configs, VCN instance can be exclusively allocated to a
partition even under CPX mode.
Signed-off-by: Lijo Lazar
Reviewed-by: James Zhu
From: Alex Hung
[ Upstream commit ecedd99a9369fb5cde601ae9abd58bca2739f1ae ]
[WHY]
dynamic memory safety error detector (KASAN) catches and generates error
messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not
support certain features which are not initialized.
[HOW]
Skip th
From: Tao Zhou
[ Upstream commit f886b49feaae30acd599e37d4284836024b0f3ed ]
SDMA_CNTL is not set in some cases, driver configures it by itself.
v2: simplify code
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/a
From: Lijo Lazar
[ Upstream commit 4b18a91faf1752f9bd69a4ed3aed2c8f6e5b0528 ]
Downgrade to debug information when IBs are skipped. Also, use dev_* to
identify the device.
Signed-off-by: Lijo Lazar
Reviewed-by: Christian König
Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
Signed-off-by
From: Lijo Lazar
[ Upstream commit f7e232de51bb1b45646e5b7dc4ebcf13510f2630 ]
VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In
certain configs, VCN instance can be exclusively allocated to a
partition even under CPX mode.
Signed-off-by: Lijo Lazar
Reviewed-by: James Zhu
From: Zhigang Luo
[ Upstream commit d06af584be5a769d124b7302b32a033e9559761d ]
If there are more than one device doing reset in parallel, the first
device will call kfd_suspend_all_processes() to evict all processes
on all devices, this call takes time to finish. other device will
start reset an
From: Kenneth Feng
[ Upstream commit 3818708e9c9712e2ba4006bc23502ee7b031bd3f ]
fix the high voltage issue after unload on smu 13.0.10
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.
From: Alex Hung
[ Upstream commit ecedd99a9369fb5cde601ae9abd58bca2739f1ae ]
[WHY]
dynamic memory safety error detector (KASAN) catches and generates error
messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not
support certain features which are not initialized.
[HOW]
Skip th
From: Tao Zhou
[ Upstream commit f886b49feaae30acd599e37d4284836024b0f3ed ]
SDMA_CNTL is not set in some cases, driver configures it by itself.
v2: simplify code
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/a
From: Yifan Zhang
[ Upstream commit 533eefb9be76c3b23d220ee18edfda8eb56cefff ]
This patch to add smu 14.0.1 support
Reviewed-by: Alex Deucher
Signed-off-by: Yifan Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file ch
From: Lijo Lazar
[ Upstream commit 4b18a91faf1752f9bd69a4ed3aed2c8f6e5b0528 ]
Downgrade to debug information when IBs are skipped. Also, use dev_* to
identify the device.
Signed-off-by: Lijo Lazar
Reviewed-by: Christian König
Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
Signed-off-by
From: Li Ma
[ Upstream commit d4396924c3d44f34d0643f650e70892e07f3677f ]
There is a new DCN veriosn 3.5.1 need to load
Signed-off-by: Li Ma
Reviewed-by: Yifan Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
Using the job pointer to check if the FLR comes from the host is wrong,
there are other reset triggers that pass NULL for job. So add a flag
explicitly for host triggered reset.
Signed-off-by: Yunxiang Li
---
v2: fix typo
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
drivers/gpu/drm/amd/
On Mon, Apr 22, 2024 at 3:52 PM Yunxiang Li wrote:
>
> Reset request from KFD is missing a check for if a reset is already in
> progress, this causes a second reset to be triggered right after the
> previous one finishes. Add the check to align with the other reset sources.
Acked-by: Alex Deucher
From: Sonny Jiang
VCN5 session info package interface changed
Signed-off-by: Sonny Jiang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vc
Reset request from KFD is missing a check for if a reset is already in
progress, this causes a second reset to be triggered right after the
previous one finishes. Add the check to align with the other reset sources.
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
Using the job pointer to check if the FLR comes from the host is wrong,
there are other reset triggers that pass NULL for job. So add a flag
explicitly for host triggered reset.
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f529a6d274b3b8c75899e949649d231298f30a32 Add linux-next specific
files for 20240422
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404221830.cjqlhldl-...@intel.com
Error
[AMD Official Use Only - General]
These two patches Looks good to me .
Reviewed by Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Monday, April 22, 2024 10:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu: add
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eD
On 2024-04-22 10:56, Christian König
wrote:
Am
22.04.24 um 15:57 schrieb Philip Yang:
To test RDMA using dummy driver on the
system without NIC/RDMA
device, the get/put dma pages pass in null device pointer, skip
t
On 2024-04-22 10:40, Christian König
wrote:
Am
22.04.24 um 15:57 schrieb Philip Yang:
Define macro MAX_SG_SEGMENT_SIZE 2GB,
because struct scatterlist length
is unsigned int, and some users of it cast to a signed int, so
From: Aric Cyr
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/displa
From: Anthony Koo
- Adjust the dmub_fw_boot_options reserved bits to be correct
Acked-by: Aurabindo Pillai
Signed-off-by: Anthony Koo
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Rodrigo Siqueira
The string dp_hdmi_dongle_signature_str already uses u8 but the string
dp_hdmi_dongle_signature_str does not. Just replace uint8_t with u8 for
dp_hdmi_dongle_signature_str.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by: Da
From: yi-lchen
[why]
VBios & Driver may have differnet pixel rate div policy.
If the policy is not same and fast boot is enabled,
it would cause the pixel rate is too high
after driver only performs stream blank & unblank.
[how]
We would keep pixel rate div setting by VBios until next mode set.
From: Sung Joon Kim
[why & how]
There are potential issues with Z8 and IPS
that need to be addressed and need to add
in missing function pointers.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/displ
From: Cruise
[Why]
Error correction was enabled in a monitor which doesn't support.
[How]
Disable error correction if it's not supported
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Cruise
Tested-by: Daniel Wheeler
---
.../display/dc/link/protocols/link_dp_phy.c | 4
From: Sung Joon Kim
[why & how]
The recout x offset was incorrect which led to
wrong viewport calculation. For stereo
side-by-side case, the slice index should be
0 for both split pipes.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel
From: Harry Wentland
HWSS set_cursor_attributes copies the stream's cursor attributes
to the hubp cursor attributes. set_cursor_position might attempt
to program the cursor attributes but will program them wrong if
they're not set correctly. We need to call HWSS set_cursor_attributes
first to ens
From: Harry Wentland
We're seeing issues when user-space tries to do an atomic update of
the primary surface, as well as the cursor. These two updates are
separate calls into DC and don't currently act as an atomic update.
This might lead to cursor updates being locked out and cursors
stuttering.
From: Joshua Aberback
This reverts commit 44739205e867
[Why]
The change being reverted incorrectly assumes that a pointer type was
intended, however copying to a new structure is correct. As well, there
is no compiler error, it was instead an error in the testing framework
being used.
Reviewed-
From: Ilya Bakoulin
Not every ASIC implements dp_set_dsc_config. Add condition to prevent
calls to unimplemented function.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Ilya Bakoulin
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 16
From: Meenakshikumar Somasundaram
[Why]
During DP tunnel creation, CM preallocates BW and reduces
estimated BW of other DPIA. CM release preallocation only
when allocation is complete. Display mode validation logic
validates timings based on bw available per host router.
In multi display setup, t
From: Hersen Wu
[Why] DSC debugfs, such as dp_dsc_clock_en_read,
use aconnector->dc_link to find pipe_ctx for display.
Displays connected to MST hub share the same dc_link.
DSC instance is from pipe_ctx. This causes incorrect
DSC instance for display connected to MST hub.
[How] Add aconnector->s
From: Nicholas Kazlauskas
[Why]
It's possible that the write hasn't fully completed by the time we
send (and flush) a command to DMCUB to notify idle to request IPS2
exit.
[How]
Perform a readback of the volatile structure into dc_dmub_srv state.
Reviewed-by: Charlene Liu
Acked-by: Aurabindo P
From: Ethan Bitnun
[Description]
- Block FPO if the max stretch refresh rate is low enough
to cause a flicker by storing the maximum safe refresh
decrease from nominal in stream.
- Brought over various Freesync Luminance functions to dc. Use these
new functions to block fpo if we will
From: George Shen
[Why]
Upon disconnecting a UHBR SST display, the disconnection and the
SetTimings to disable the display can occur such that link_set_dpms_off
occurs after the disconnection has already processed
(link->type is dc_connection_none). Thus, the AUX related
operations should be skip
From: Gabe Teeger
New request from KMD/VBIOS in order to support new UMA carveout
model. This fixes a null dereference from accessing
Ctx->dc_bios->integrated_info while it was NULL.
DAL parses through the BIOS and extracts the necessary
integrated_info but was missing a case for the new BIOS
ve
From: Michael Strauss
[WHY]
Avoid race condition which puts LTTPR into bad state during UHBR LT.
[HOW]
Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
Tested-by: Daniel Wheeler
---
From: Sung-huai Wang
[Why]
TCON data is corrupted after electro static discharge test.
Once the TCON data get corrupted, they will get themselves
reset and send HPD_IRQ to source side.
[How]
Support HPD_IRQ for internal link, and restore the PSR/Replay setup.
Reviewed-by: Robin Chen
Acked-by:
From: Sung Joon Kim
[why & how]
Need to update the function pointers that
perform the power up and down sequence
to reuse the modified sequence as a requirement.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
drivers/gp
From: Swapnil Patel
[Why & How]
Currently DCN315 clk manager is missing code to enable/disable dtbclk.
Because of this, "optimized_required" flag is constantly set
and this prevents FreeSync from engaging for certain high bandwidth
display Modes which require DTBCLK.
Reviewed-by: Dmytro Laktyus
From: Natanel Roizenman
[WHY]
When switching from "Extend" to "Second Display Only" we sometimes
call resource_get_otg_master_for_stream on a stream for the eDP,
which is disconnected. This leads to a null pointer dereference.
[HOW]
Added a null check in dc_resource.c/resource_log_pipe_topology_
From: Dennis Chan
When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.
Reviewed-by: ChunTao Tso
Acked-by: Aurabindo Pillai
Signed-off-by: Dennis Chan
Tested-by: Daniel
From: Rodrigo Siqueira
Drop unnecessary semicolon that can create a problem of double semicolon
in some compilers.
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h | 3 +--
1
From: Rodrigo Siqueira
This commit add some DPCX IRQ types.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types
From: Rodrigo Siqueira
This commit adds, updates, and removes some of the comments used in the
DC code.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h| 2 +-
.../gpu/drm/amd/display/dc/dpp/dcn201/
From: Rodrigo Siqueira
In the DCN20 resource initialization, ensure that DMCUB support starts
configured as true.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
1 file changed, 1 i
From: Rodrigo Siqueira
Add some missing HDCP registers to be used in DCN35.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn35/dcn35_dio_link_encoder.h| 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff -
From: Rodrigo Siqueira
This commit address some small code style issues in DC.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c| 3 +--
drivers/gpu/drm/amd/display/dc/dm_helpers.h
From: Rodrigo Siqueira
This commit reorganizes the order in which some control registers are
presented to make it easier to identify the operations based on the
hardware doc.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/d
From: George Shen
Theoretically rare corner case where ceil(Y) results in rounding up to
an integer. If this happens, the 1 should be carried over to the X
value.
CC: sta...@vger.kernel.org
Reviewed-by: Rodrigo Siqueira
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
.../drm/amd/dis
From: Rodrigo Siqueira
This commit removes some unnecessary code and makes the required
adjustments to replace other parts of the code with a short option.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce/dce_transfor
From: Dmytro Laktyushkin
Headless dp 2.0 will take longer to update.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Rodrigo Siqueira
This commit add some missing HDMI control registers to DCN3x.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 3 +++
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
From: Rodrigo Siqueira
Add TMDS balancer control to the list of available encoder registers for
DCN 30.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h | 3 ++-
1 file changed, 2 insertions
From: Rodrigo Siqueira
DCN3.0 supports some specific DWB debug registers that are not exposed
yet. This commit just adds the missing registers.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h | 14 +
From: Rodrigo Siqueira
This commit add some missing debug registers for DPCS and RDPC debug.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 5 +++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 2 ++
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
==
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.214.0
Aric Cyr (1):
drm/am
Am 18.04.24 um 18:10 schrieb Alex Deucher:
On Thu, Mar 21, 2024 at 10:37 AM Christian König
wrote:
Am 21.03.24 um 15:12 schrieb Tvrtko Ursulin:
On 21/03/2024 12:43, Christian König wrote:
This reverts drm/amdgpu: fix ftrace event amdgpu_bo_move always move
on same heap. The basic problem here
Am 16.04.24 um 10:51 schrieb Prike Liang:
Add the amdgpu buffer object move speed metrics.
What should that be good for? It adds quite a bunch of complexity for a
feature we actually want to deprecate.
Regards,
Christian.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu
Am 22.04.24 um 15:57 schrieb Philip Yang:
To test RDMA using dummy driver on the system without NIC/RDMA
device, the get/put dma pages pass in null device pointer, skip the
dma map/unmap resource and sg table to avoid null pointer access.
Well that is completely illegal and would break IOMMU.
Am 22.04.24 um 16:40 schrieb Alex Deucher:
On Mon, Apr 22, 2024 at 9:00 AM Christian König
wrote:
Am 22.04.24 um 14:33 schrieb Qiang Ma:
On Mon, 22 Apr 2024 11:40:26 +0200
Christian König wrote:
Am 22.04.24 um 07:26 schrieb Qiang Ma:
Some boards(like Oland PRO: 0x1002:0x6613) seem to have
Am 22.04.24 um 15:57 schrieb Philip Yang:
Define macro MAX_SG_SEGMENT_SIZE 2GB, because struct scatterlist length
is unsigned int, and some users of it cast to a signed int, so every
segment of sg table is limited to size 2GB maximum.
For contiguous VRAM allocation, don't limit the max buddy blo
On Mon, Apr 22, 2024 at 9:00 AM Christian König
wrote:
>
> Am 22.04.24 um 14:33 schrieb Qiang Ma:
> > On Mon, 22 Apr 2024 11:40:26 +0200
> > Christian König wrote:
> >
> >> Am 22.04.24 um 07:26 schrieb Qiang Ma:
> >>> Some boards(like Oland PRO: 0x1002:0x6613) seem to have
> >>> garbage in the up
We can't use a shared fence location because each transaction
should be considered independently.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 12
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 21 +++
As we use wb slots more dynamically, we need to lock
access to avoid racing on allocation or free.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
dif
On 2024-04-22 09:51, Rodrigo Siqueira wrote:
> This reverts commit 5ea4581611d14a6a0e8df40965802ec7bee9c671.
>
> This change must be reverted since it caused soft hangs when changing
> the refresh rate to 122 & 144Hz when using a 7000 series GPU.
>
> Reported-by: Mark Broadworth
> Cc: Daniel Whe
On Mon, Apr 22, 2024 at 10:12 AM Sathishkumar S
wrote:
>
> jpeg ip version v2.1 and higher supports 16kx16k resolution decode
>
> Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c| 6 +++---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
> driver
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