On 11/16/2023 2:39 AM, Mario Limonciello wrote:
On 11/15/2023 11:04, Mario Limonciello wrote:
On 11/14/2023 21:23, Lazar, Lijo wrote:
On 11/15/2023 1:37 AM, Mario Limonciello wrote:
The USB4 spec specifies that PCIe ports that are used for tunneling
PCIe traffic over USB4 fabric will be h
This patch is to update lsdma headers.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
.../asic_reg/lsdma/lsdma_6_0_0_offset.h | 48 ++
.../asic_reg/lsdma/lsdma_6_0_0_sh_mask.h | 452 ++
2 files changed, 500 insertions(+)
diff --git a/drivers/gpu/drm/amd/inclu
Add a module parameter for enabling LSDMA, defalt disable it until
proven stable. The module parameter is used to enable LSDMA ring
mode, and switch paging, system buffer management from SDMA to LSDMA.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
This patch is to add ring mode support for lsdma.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 40 +
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 33 +-
drivers/gpu/drm/amd/am
LSDMA ring mode doesn't support doorbell.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 45280fb0e00c..2
Tag VRAM BOs that do not have a VA with a unique Id, a 128-bit
UUID. This unique Id is used to distinguish BOs that might
otherwise be of same size. Checkpoint and restore assumes
that these BOs are not imported into a DRM device that is
accessible either from current process or its parent or
child
This patch is to add lsdma hw ip definition.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 15 +++
drivers/gpu/drm/amd/include/a
This patch is to add lsdma interrupt src id.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
.../include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h
b/drivers/gpu/d
This series implements LSDMA ring mode, creates LSDMA ring and implement
amdgpu ring related functions. Introduce a new module parameter amdgpu_lsdma
to enable LSDMA, switch buffer and paging funcs from SDMA to LSDMA. It changes
amdgpu driver buffer operations to LSDMA, changes default page table u
From: Ivan Lipski
This commit caused a page fault issue on RX7000 series GPU.
It would occur when running different IGT tests, including
kms_properties*
kms_cursor_legacy*
kms_prop_blob@blob*
It would also occur on desttop after some time of idling.
The easiest fix for it seems to revert it.
T
On 11/15/2023 11:04, Mario Limonciello wrote:
On 11/14/2023 21:23, Lazar, Lijo wrote:
On 11/15/2023 1:37 AM, Mario Limonciello wrote:
The USB4 spec specifies that PCIe ports that are used for tunneling
PCIe traffic over USB4 fabric will be hardcoded to advertise 2.5GT/s and
behave as a PCIe G
On Wed, Nov 15, 2023 at 11:39 PM Lee, Alvin wrote:
>
> This change has a DMCUB dependency - are you able to update your DMCUB
> version as well?
>
I can confirm this issue was gone after updating firmware.
❯ dmesg | grep DMUB
[ 11.496679] [drm] Loading DMUB firmware via PSP: version=0x0700230
From: Zhongwei
[WHY]
Handover from DMUB to driver does not perform link rate toggle.
It might cause link training failure for boot up.
[HOW]
Force toggle rate wa for first link train.
link->vendor_specific_lttpr_link_rate_wa should be zero then.
Cc: sta...@vger.kernel.org # 6.1+
Reviewed-by: Mi
From: Nicholas Kazlauskas
[Why]
Some panels with residency period of 2054 exhibit flickering with
Z8 at the end of the frame.
[How]
As a workaround, increase the limit to block these panels.
Cc: sta...@vger.kernel.org # 6.1+
Reviewed-by: Syed Hassan
Acked-by: Hamza Mahfooz
Signed-off-by: Nich
From: Anthony Koo
- Add a tracing framework, to measure duration, execution count and
longest duration of main loop/vsync interrupt work
GPINT command is used to start/stop the measurements.
Acked-by: Hamza Mahfooz
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_c
From: Alvin Lee
[Description]
- To reduce vlevel further, we can try to apply subvp on
configs that already support p-state since the natural
p-state support may not allow for DPM0.
- Add code to try subvp to reduce UCLK DPM level further
if already supported, but don't use subvp if it does
From: Sung Joon Kim
[why]
We have dynamic power control in driver but
should be ignored when power is forced on.
[how]
Bypass any power control when it's forced on.
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hamza Mahfooz
Signed-off-by: Sung Joon Kim
---
.../drm/a
From: Aric Cyr
This version brings along the following:
- DCN314 fixes
- DCN32 fixes
- DCN35 fixes
- DML2 fixes
- eDP fixes
- HDR fixes
- MST fixes
- Replay fixes
- SubVP support for more configs
Acked-by: Hamza Mahfooz
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1
From: Taimur Hassan
[Why]
A number of DML parameters related to HostVM were either missing or
being set incorrectly, which may cause inaccuracies in calculating
margins and determining BW limitations.
[How]
Correct these values where needed and populate the missing values.
Cc: sta...@vger.kerne
From: Taimur Hassan
[Why]
There are a number of instances where we convert HostVMMinPageSize or
GPUVMMinPageSize from bytes to KB by dividing (rather than multiplying) and
vice versa.
Additionally, in some cases, a parameter is passed through DML in KB but
later checked as if it were in bytes.
C
From: Nicholas Kazlauskas
[Why]
The new table doesn't have an implicit mapping between Fclk SOC voltage
and MemClk and it currently builds the table off of number of Fclk
states rather than DcfClock states.
The DML table in use is not correct for functionality or power and
does not align with ou
From: Taimur Hassan
[Why]
Prevent overwrite of dc->config.use_default_clock_table, as it should be
pre-configured.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hamza Mahfooz
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file changed,
From: Parandhaman K
[why]
Move all optc files to unique
folder optc.
[how]
creating optc repo in dc, and moved the dcnxx_optc.c and .h files into
corresponding new folders inside the optc and cleared the linkage
errors by adding relative paths in the Makefile.template.
Reviewed-by: Martin Leung
From: Camille Cho
[Why]
Remove the brightness cache in DC. It uses a single value to represent
the brightness for both SDR and HDR mode. This leads to flash in HDR
on/off. It also unconditionally programs brightness as in HDR mode. This
may introduce garbage on SDR mode in miniLED panel.
[How]
S
From: Gabe Teeger
This reverts commit c2925d905ede9f7023168857e8f488136e56a1d4.
[why]
Flickering observed. Regression search pointed to this being
the offending commit.
Reviewed-by: Charlene Liu
Reviewed-by: Yihan Zhu
Acked-by: Hamza Mahfooz
Signed-off-by: Gabe Teeger
---
drivers/gpu/drm/a
From: Meenakshikumar Somasundaram
[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.
[How]
To call dc_trigger_sync() after clock update to sync otgs again.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hamza Mahfooz
Signed-off-by: Meenakshikumar Som
From: Wayne Lin
[Why]
MST relevant variables are maintained at drm side. As the result, we
still have to call drm_dp_remove_payload_part2() to update the relevant
values regardless the link is under mst mode or not. We used to have a
workaround patch to tackle this: commit 3d8fcc6740c9 ("drm/amd/
From: Dennis Chan
[why]
If Panel max link off frame count is low, it will cause low residency
for Replay, then Disabled timing sync check in Full screen Video Case.
Reviewed-by: Robin Chen
Acked-by: Hamza Mahfooz
Signed-off-by: Dennis Chan
---
drivers/gpu/drm/amd/display/dc/dc_types.h |
From: Alvin Lee
[Description]
- Previously SubVP would never be selected on 1080p60 displays because
it has too much vactive margin. However, implement a change to allow
it like how 1440p60 is allowed.
- Add a new struct such that we have a list of allowed modes for
enabling subvp with vact
From: Nicholas Kazlauskas
[Why]
Flickering occurs on DRR supported panels when engaged in DRR due to
min_dst_y_next becoming larger than the frame size itself.
[How]
In general, we should be able to enter Z8 when this is engaged but it
might be a net power loss even if the calculation wasn't bug
From: Max Tseng
[Why]
Sending certain Frameupdate number for Replay Power Evaluation
Reviewed-by: Dennis Chan
Acked-by: Hamza Mahfooz
Signed-off-by: Max Tseng
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
.../gpu/drm/amd/display/dc/dce/dmub_replay.h | 2 +-
.../link/protocols/l
From: Alvin Lee
[Description]
If during driver init stage there are greater than 20
intermediary voltage states while constructing the SOC
BB we could hit issues because we will index outside of the
clock_limits array and start overwriting data. Increase the
total number of states to 40 to avoid
From: Alvin Lee
[Description]
When choosing which dummy p-state latency to use, we
need to use the DRAM speed from validation. The DRAMSpeed
DML variable can change because we use different input
params to DML when populating watermarks set B.
Cc: sta...@vger.kernel.org # 6.1+
Reviewed-by: Samso
From: Nicholas Kazlauskas
[Why]
We've updated the table but the values aren't being reflected in DML2
calculation.
[How]
Pass them into the bbox overrides.
Reviewed-by: Jun Lei
Acked-by: Hamza Mahfooz
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.
From: Max Tseng
Augment the function to allow send different format data in different
use case.
Reviewed-by: Dennis Chan
Acked-by: Hamza Mahfooz
Signed-off-by: Max Tseng
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
From: Michael Strauss
[WHY]
Currently DCN35 does not spread DPREFCLK
[HOW]
Remove hardcoded table with nonzero caps
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hamza Mahfooz
Signed-off-by: Michael Strauss
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 22 ---
1 file chan
From: Nicholas Kazlauskas
[Why]
We can override SR watermarks but not Z8 ones.
[How]
Add new parameters for Z8 matching the SR ones and feed them into the
states.
These also weren't being applied to every state, so make sure that
we loop over and update all SOC states if given an override.
Rev
From: Bhuvana Chandra Pinninti
[why]
To refactor DSC and make DSC files unit testable.
[how]
moved the dcnxx_dsc.c and .h files
into corresponding dcn folders inside
the dsc and cleared the linkage errors.
Reviewed-by: Wenjing Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Bhuvana Chandra Pinni
From: Ilya Bakoulin
[Why]
Wrong function is used to translate LUT values to HW format, leading to
visible artifacting in some cases.
[How]
Use the correct cm3_helper function.
Cc: sta...@vger.kernel.org # 6.1+
Reviewed-by: Krunoslav Kovac
Acked-by: Hamza Mahfooz
Signed-off-by: Ilya Bakoulin
From: Wenjing Liu
[why]
In dcn32 DML pipes are ordered the same as dc pipes but only for used
pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices
would be 0 and 1 respectively. However
update_pipe_slice_table_with_split_flags doesn't skip indices for free
pipes. This causes us
From: Wenjing Liu
[why]
In the new pipe resource management logic, the special handling for
stereo timings is missing.
This commit implements the same stereo timings handling as old
pipe resource management code.
Reviewed-by: Chaitanya Dhere
Acked-by: Hamza Mahfooz
Signed-off-by: Wenjing Liu
From: Wenjing Liu
[why]
When ODM slice count is changed, otg master pipe's pixel clock params is
no longer valid as the value is dependent on ODM slice count.
Reviewed-by: Chaitanya Dhere
Acked-by: Hamza Mahfooz
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c
From: Nicholas Kazlauskas
[Why & How]
Update to the new values per HW team request. Affects both stutter
and z8.
Reviewed-by: Charlene Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Nicholas Kazlauskas
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 32 +--
.../drm/amd/displa
From: Ian Chen
If the link requests to skip implicit eDP power control, we should honor
that request.
Reviewed-by: Robin Chen
Acked-by: Hamza Mahfooz
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
From: Nicholas Kazlauskas
[Why]
DML2 means that the dcn3x policy for calculating z-state support
no longer runs from validate_bandwidth.
This means we are unconditionally allowing Z8, the hardware default.
[How]
Port the policy over to DCN35, but with a few modifications:
- Don't use min_dst_y_
From: Dennis Chan
[why]
To support dynamic switching for Replay timing sync mechanism.
Reviewed-by: ChunTao Tso
Acked-by: Hamza Mahfooz
Signed-off-by: Dennis Chan
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 10
.../gpu/drm/amd/display/dc/dce/dmub_replay.h | 3 +++
drivers/
From: Alvin Lee
When waiting for the ACK for INBOX0 message,
we have to ensure to include the udelay
for proper wait time
Cc: sta...@vger.kernel.org # 6.1+
Reviewed-by: Samson Tam
Acked-by: Hamza Mahfooz
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 +
1 fi
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DCN314 fixes
* DCN32 fixes
* DCN35 fixes
* DML2 fixes
* eDP fixes
* HDR fixes
* MST fixes
* Replay fixes
* SubVP support for more configs
Alvin Lee (5):
drm/amd/display: Include udelay when waiting for INBOX0 AC
[AMD Official Use Only - General]
This change has a DMCUB dependency - are you able to update your DMCUB version
as well?
This version mismatch issue is something I'll need to fix in driver for Linux.
Thanks,
Alvin
-Original Message-
From: Mikhail Gavrilov
Sent: Wednesday, November 1
On 2023-10-05 13:15, Melissa Wen wrote:
> Add AMD pre-defined transfer function property to default DRM CRTC gamma
> to convert to wire encoding with or without a user gamma LUT. There is
> no post-blending regamma ROM for pre-defined TF. When setting Gamma TF
> (!= Identity) and LUT at the same
On 2023-10-05 13:15, Melissa Wen wrote:
> From: Joshua Ashton
>
> Blend 1D LUT or a pre-defined transfer function (TF) can be set to
> linearize content before blending, so that it's positioned just before
> blending planes in the AMD color mgmt pipeline, and after 3D LUT
> (non-linear space).
On 2023-10-05 13:15, Melissa Wen wrote:
> On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
> delinearizing and/or normalizing the color space before applying a 3D
> LUT. Add pre-defined transfer function to enable delinearizing content
> with or without shaper LUT, where AMD c
On 2023-10-05 13:15, Melissa Wen wrote:
> From: Joshua Ashton
>
> Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
> transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
> least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
> nits for
On 2023-10-05 13:15, Melissa Wen wrote:
> Brief documentation about pre-defined transfer function usage on AMD
> display driver and standardized EOTFs and inverse EOTFs.
>
> v3:
> - Document BT709 OETF (Pekka)
> - Fix description of sRGB and pure power funcs (Pekka)
>
> v4:
> - Add description
On 2023-10-05 13:15, Melissa Wen wrote:
> Instead of relying on color block names to get the transfer function
> intention regarding encoding pixel's luminance, define supported
> Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that
> includes pure gamma or standardized transfer fu
On Wed, Nov 15, 2023 at 11:14 PM Hamza Mahfooz wrote:
>
> What version of DMUB firmware are you on?
> The easiest way to find out would be using the following:
>
> # dmesg | grep DMUB
>
Sapphire AMD Radeon RX 7900 XTX PULSE OC:
❯ dmesg | grep DMUB
[ 14.341362] [drm] Loading DMUB firmware via PS
On 11/15/23 13:10, Mikhail Gavrilov wrote:
On Tue, Nov 14, 2023 at 11:03 PM Mikhail Gavrilov
wrote:
On Tue, Nov 14, 2023 at 3:55 PM Mikhail Gavrilov
wrote:
Hi,
Yesterday came the 6.7-rc1 kernel.
And surprisingly it turned out it is not working with my LG C3.
I use this OLED TV as my primary
On Tue, Nov 14, 2023 at 11:03 PM Mikhail Gavrilov
wrote:
>
> On Tue, Nov 14, 2023 at 3:55 PM Mikhail Gavrilov
> wrote:
> >
> > Hi,
> > Yesterday came the 6.7-rc1 kernel.
> > And surprisingly it turned out it is not working with my LG C3.
> > I use this OLED TV as my primary monitor.
> > After log
On 11/15/2023 04:40, Mika Westerberg wrote:
Hi Mario,
On Tue, Nov 14, 2023 at 02:07:53PM -0600, Mario Limonciello wrote:
USB4 routers support a feature called "PCIe tunneling". This
allows PCIe traffic to be transmitted over USB4 fabric.
PCIe root ports that are used in this fashion can be dis
On 11/14/2023 21:23, Lazar, Lijo wrote:
On 11/15/2023 1:37 AM, Mario Limonciello wrote:
The USB4 spec specifies that PCIe ports that are used for tunneling
PCIe traffic over USB4 fabric will be hardcoded to advertise 2.5GT/s and
behave as a PCIe Gen1 device. The actual performance of these por
Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1373: warning: Function parameter or
member 'xcc_mask' not described in 'amdgpu_vm_flush_compute_tlb'
Cc: Felix Kuehling
Cc: Christian König
Cc: Alex Deucher
Cc: "Pan, Xinhui"
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Updated xcc
On 2023-11-15 2:01, Christian König wrote:
Felix that looks a bit fishy to me, can you take a look?
Why are we giving the xcc_mask as parameter here? IIRC the partition a
VM is used with is fixed because the page tables are created
individually for each partition.
Thanks,
Christian.
Am 12.1
On 11/11/2023 4:04 AM, Mario Limonciello wrote:
When bandwidth limits are looked up using pcie_bandwidth_available()
virtual links such as USB4 are analyzed which might not represent the
real speed. Furthermore devices may change speeds autonomously which
may introduce conditional variation to
Am 14.11.23 um 21:07 schrieb Mario Limonciello:
pci_is_thunderbolt_attached() looks at the hierarchy of the PCIe device
to determine if any bridge along the way has the is_thunderbolt bit set.
This bit will only be set when one of the devices in the hierarchy is an
Intel Thunderbolt device.
Howe
The following patch will fix a minor issue where a debug message is
referencing an struct that has just being checked whether is null or
not. This has been noticed by using coccinelle, in the following output:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:540:25-29: ERROR:
aconnector
On 2023-11-14 23:01, Hamza Mahfooz wrote:
On 11/14/23 10:27, José Pekkarinen wrote:
The following patch will fix a minor issue where a debug message is
referencing an struct that has just being checked whether is null or
not. This has been noticed by using coccinelle, in the following
output:
Hi!
> > > From: Alex Deucher
> > >
> > > [ Upstream commit 49afe91370b86566857a3c2c39612cf098110885 ]
> > >
> > > For pptable structs that use flexible array sizes, use flexible arrays.
> > >
> > > Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2039926
> > > Reviewed-by: Mario Limo
Hi all,
just took out 6.7.0-rc1 for a spin (including latest upstream linux-firmware).
GPU is an RX 7800 XT. I'm getting a constant flood of errors in dmesg.
Otherwise I don't observe any out of place behavior on linux. However, when I
reboot into Windows I get a low resolution display (I'm assum
This patch will address the following coccinelle warning where a pointer
is compared to 0 instead of NULL.
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c:5423:19-20: WARNING
comparing pointer to 0
Fixes: 7966f319c66d9 ("drm/amd/display: Introduce DML2")
Signed-off-by: José Pekkarinen
-
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