Am 25.10.23 um 20:45 schrieb Felix Kuehling:
On 2023-10-25 02:12, Christian König wrote:
Am 24.10.23 um 21:20 schrieb David Francis:
dmaunmap can call ttm_bo_validate, which expects the
ttm dma_resv to be held.
Well first of all the dma_resv object isn't related to TTM.
Acquire the locks i
Am 25.10.23 um 19:19 schrieb Alex Deucher:
Rather than doing this in the IP code for the SDMA paging
engine, move it up to the core device level init level.
This should fix the scheduler init ordering.
v2: drop extra parens
v3: drop SDMA helpers
Tested-by: Luben Tuikov
Signed-off-by: Alex Deuc
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Thursday, October 26, 2023 12:37
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice
Subject: [PATCH] drm/amdgpu: Retrieve CE count from ce_count_l
Retrieve correctable error count from ce_count_lo_chip instead of
mca_umc_status.
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/umc_v8_10.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
b/drivers/gpu/drm/amd/am
Hi Dave, Sima,
One last fix for 6.6.
The following changes since commit 05d3ef8bba77c1b5f98d941d8b2d4aeab8118ef1:
Linux 6.6-rc7 (2023-10-22 12:11:21 -1000)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.6-2023-10-25
for you to
-Original Message-
From: Kenneth Feng
Sent: Thursday, October 26, 2023 11:34 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Wang, Yang(Kevin)
; Feng, Kenneth
Subject: [PATCH v2] drm/amd/pm: fix the high voltage and temperature issue
fix the high voltage and temperatur
fix the high voltage and temperature issue after the driver is unloaded on smu
13.0.0,
smu 13.0.7 and smu 13.0.10
v2 - fix the code format and make sure it is used on the unload case only.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 25 ++
drivers
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Thursday, October 26, 2023 10:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Li, Candice
Subject: [PATCH] drm/amdgpu: Identify data parity error corrected in replay mode
The current code checks sriov vf flag multiple times when creating
hwmon sysfs. So fix it.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/
drop this one for some format issue.
I will send a new version.
Regards,
Ma Jun
On 10/26/2023 10:45 AM, Ma Jun wrote:
> The current code checks sriov vf flag multiple times when creating
> pm sysfs. So fix it and optimize related code here.
>
> Signed-off-by: Ma Jun
> ---
> drivers/gpu/drm/amd
The current code checks sriov vf flag multiple times when creating
pm sysfs. So fix it and optimize related code here.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/am
Use ErrorCodeExt field to identify data parity error in replay mode.
Signed-off-by: Candice Li
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 32 ++
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
Hi Sagar,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master v6.6-rc7 next-20231025]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 38 --
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 40 +--
drivers/gpu/drm/am
amdgpu_virt_kiq_reg_write_reg_wait is hardcoded to use MEC engine 0.
Add xcc_inst as a parameter to allow it to use different MEC engines.
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu/
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.
Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC
and amdgpu_device_xcc_wreg/rreg to to use the new xcc_id parameter.
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdgpu_device_xcc_wreg/rreg instead of changing p
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.
Add xcc instance parameter to them.
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 6 +++---
The "rlcg_reg_access_supported" flag is missing. Add it back in.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 41bbabd9ad4d..386804f
On 2023-10-25 02:12, Christian König wrote:
Am 24.10.23 um 21:20 schrieb David Francis:
dmaunmap can call ttm_bo_validate, which expects the
ttm dma_resv to be held.
Well first of all the dma_resv object isn't related to TTM.
Acquire the locks in amdgpu_amdkfd_gpuvm_dmaunmap_mem.
Because t
Rather than doing this in the IP code for the SDMA paging
engine, move it up to the core device level init level.
This should fix the scheduler init ordering.
v2: drop extra parens
v3: drop SDMA helpers
Tested-by: Luben Tuikov
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_d
On Tue, Oct 24, 2023 at 11:57 PM Kenneth Feng wrote:
>
> fix the high voltage and temperature issue after the driver is unloaded on
> smu 13.0.0,
> smu 13.0.7 and smu 13.0.10
> v2 - fix the code format and make sure it is used on the unload case only.
>
> Signed-off-by: Kenneth Feng
> ---
> dri
Add kernel documentation for the dc_stream_forward_crc_window
Signed-off-by: Sagar Vashnav
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 17
Rather than doing this in the IP code for the SDMA paging
engine, move it up to the core device level init level.
This should fix the scheduler init ordering.
v2: drop extra parens
Tested-by: Luben Tuikov
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +
On 10/4/2023 6:26 AM, Victor Lu wrote:
WREG32_RLC does not specify the correct XCC so the RLCG interface does
not work.
Define WREG32_RLC_XCC to be like WREG32_RLC but include a parameter to
specify the XCC.
v2: Add new macro WREG32_RLC_XCC instead of modifying exiting WREG32_RLC
macro
refine the amdgpu_ucode_request() api to support formatting type name as
input.
NOTE:
The new refined API is compatible with previous usage case and has no
functional impact.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 8 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_
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