On 8/12/2023 4:03 PM, Asad Kamal wrote:
1) Update pcie link speed for smu v13_0_6 from correct register
2) Populate gpu metric table with pcie link speed rather than
gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7
v2:
Update ESM register address
Used macro to convert pcie gen to speed
Si
On 8/12/2023 1:53 PM, Christian König wrote:
Am 11.08.23 um 08:02 schrieb Lijo Lazar:
Presently, there are multiple clients of reset like RAS, job timeout,
KFD hang
detection and debug method. Instead of each client maintaining a work
item,
reset work pool is moved to reset domain. When a cl
On 8/12/2023 6:14 PM, James Zhu wrote:
On 2023-08-11 21:39, Lazar, Lijo wrote:
[AMD Official Use Only - General]
A dynamic partition switch could happen later. The switch could still
be successful in terms of hardware,
[JZ] Only ignore render node assignment, and remove visibility in us
Fixes the following coccicheck:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2482:16-17: WARNING opportunity for
min()
min() macro is defined in include/linux/minmax.h. It avoids multiple
evaluations of the arguments when non-constant and performs strict
type-checking.
Cc: Guchun Chen
Cc: Christian
Fixes the following coccicheck:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2427:16-17: WARNING opportunity for
min()
min() macro is defined in include/linux/minmax.h. It avoids multiple
evaluations of the arguments when non-constant and performs strict
type-checking.
Cc: Guchun Chen
Cc: Christian
On 2023-08-11 21:39, Lazar, Lijo wrote:
[AMD Official Use Only - General]
A dynamic partition switch could happen later. The switch could still
be successful in terms of hardware,
[JZ] Only ignore render node assignment, and remove visibility in user
space, xcp continues to be generated as
1)Update addresses of PCIE link width registers
for smu v13.0.6
2)Update PCIE link width format used to populate gpu metrics table
for smu v13.0.6
v2:
Removed ESM register update
Signed-off-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 10 --
1 file changed,
1) Update pcie link speed for smu v13_0_6 from correct register
2) Populate gpu metric table with pcie link speed rather than
gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7
v2:
Update ESM register address
Used macro to convert pcie gen to speed
Signed-off-by: Asad Kamal
---
drivers/gpu/drm/
Am 11.08.23 um 08:02 schrieb Lijo Lazar:
Presently, there are multiple clients of reset like RAS, job timeout, KFD hang
detection and debug method. Instead of each client maintaining a work item,
reset work pool is moved to reset domain. When a client makes a recovery
request,
a work item is all
