[Public]
Reviewed-by: Guchun Chen
Regards,
Guchun
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Wednesday, August 9, 2023 3:14 PM
> To: Koenig, Christian ; Deucher, Alexander
> ; Chen, Guchun ;
> Pan, Xinhui
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@li
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Lijo
> Lazar
> Sent: Friday, August 11, 2023 1:18 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Ma, Le
> ; Kamal, Asad ; Zhang, Hawking
>
> Subject: [PATCH 2/4] drm/amdgpu: Add bootloader status check
>
> Add
Add API which queues a work to reset domain and waits for it to finish.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 18 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 4
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
[AMD Official Use Only - General]
This patch is :
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: amd-gfx On Behalf Of Tim Huang
Sent: Friday, August 11, 2023 1:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Zhang, Jesse(Jie) ;
If reset is already done as part of recovery, set flags to cancel all
pending work items in the reset domain. Also, drop unused functions.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 6 --
2 files changed,
Add a TDR queue for rings to handle job timeouts. Ring's scheduler will
use this queue to for running job timeout handlers. Timeout handler will
then use the appropriate reset domain to handle recovery.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu
Move recovery handlers to schedule reset work. Make use of the workpool
in the reset domain and delete the individual work items.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 32 +-
drivers/gpu/drm/amd/amdgp
Presently, there are multiple clients of reset like RAS, job timeout, KFD hang
detection and debug method. Instead of each client maintaining a work item,
reset work pool is moved to reset domain. When a client makes a recovery
request,
a work item is allocated by the reset domain and queued for e
Add a work pool to reset domain. The work pool will be used to schedule
any task in the reset domain. If on successful reset of the domain
indicated by a flag in reset context, all work that are queued will be
drained. Their work handlers won't be executed.
Signed-off-by: Lijo Lazar
---
drivers/
Align the SMU driver interface version with PMFW to
suppress the version mismatch message on driver loading.
Signed-off-by: Tim Huang
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/sw
Implement the wait for bootloader call back for PSP v13.0 ASICs. Only
for ASICs with PSP v13.0.6, it needs an additional check for VBIOS
mailbox status.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
Tested-by: Asad Kamal
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.
For APUs with SMU v13.0.6, mode-2 reset is kept as default and for
others mode-1 is the default reset method.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
Tested-by: Asad Kamal
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
drivers/gpu/drm/a
Add a function to wait till bootloader has reached steady state.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
Tested-by: Asad Kamal
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 11 ++
BACO dummy mode could be set under reset conditions and that affects
framebuffer access. Check If baco dummy mode is set, unset it if so.
Signed-off-by: Lijo Lazar
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
Tested-by: Asad Kamal
---
drivers/gpu/drm/amd/amdgpu/nbi
The series adds mode-1 reset support to SMU v13.0.6 SOCs. For now, it's used as
the default reset method on dGPUs with SMU v13.0.6. Presently, reset takes
longer than expected. Hence a method is added to check the bootloader status
after reset. It checks if bootloader has set mailbox ready bit whi
[AMD Official Use Only - General]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Kenneth Feng
Sent: Friday, August 11, 2023 12:28 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth
Subject: [PATCH] drm/amd/pm: add unique_id for gc 11.0.3
drm/amd/pm: add uniqu
drm/amd/pm: add unique_id for gc 11.0.3
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5aed023f7402..c69701da94ea 100644
--- a/drivers/gpu/drm/am
For ASICs with GC v9.4.3, determine the vendor information from scratch
register.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/am
Some ASICS only offer one type of power attribute, so in the visible
callback check whether the attributes are supported and hide if not
supported.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm
Vega20 can offer average power in some versions of the PMFW and current
power in others.
Signed-off-by: Mario Limonciello
---
.../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hw
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 +-
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ++--
dr
The average power for the GPU metrics sysfs file contains the input
power not the average power. The member that is set is called average
power though, so correct it to the right value.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 2 +-
1 file chan
aldebaran_get_gpu_power() is only called by one place and just calls
aldebaran_get_smu_metrics_data(), so drop the helper.
Signed-off-by: Mario Limonciello
---
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/d
Some GPUs have been overloading average power values and input power
values. To disambiguate these, introduce a new
`AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input
power update to use this instead of average power.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/include
Aldebaran can only return average socket power for the first die.
The other dies return 0. Instead of returning a bad value, return
-EOPNOTSUPP so that the attribute will be hidden.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 7 ---
1 file chang
Many sensor function have a lot of boilerplate checks. Move these
into a generic amdgpu_hwmon_get_sensor_generic() instead.
No intended functional changes.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 321 -
1 file changed, 88 insertions
Some GPUs provide support for current power, some average power,
and some both. To be able to support all these combinations,
introduce a new attribute.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 17 +
1 file changed, 17 insertions(+)
diff --git a
[Public]
Sounds good.
I'd also change:
>> KFD currently relies on MEC FW to clear tcp watch control
>> register by sending MAP_PROCESS packet with 0 of field
>> tcp_watch_cntl to HWS, but if the queue is suspended, the
>> packet will not be sent and the previous value will be
>>>
I will change title to "drm/amdkfd: workaround address watch clearing
bug for gfx v9.4.2". is it OK?
Regards,
Eric
On 2023-08-10 18:25, Kim, Jonathan wrote:
[Public]
Yeah this is a recent bug so this workaround is new. More rigorous tests
revealed this is probably a miss on the FW side. We
There is not UNMAP_QUEUES command sending for queue preemption because
the queue is suspended and test is closed to the end. Function
unmap_queue_cpsch will do nothing after that.
The workaround is new and only for gfx v9.4.2, because debugger tests
has changed to check if all address watch po
[Public]
Yeah this is a recent bug so this workaround is new. More rigorous tests
revealed this is probably a miss on the FW side. We explicitly requested
UNMAP_QUEUES unconditionally invalidate watch controls during the beginning of
design to prevent any watch point racing.
Note GFX11 MES c
I think Jon is suggesting that the UNMAP_QUEUES command should clear the
address watch registers. Requesting such a change from the the HWS team
may take a long time.
That said, when was this workaround implemented and reviewed? Did I
review it as part of Jon's debugger upstreaming patch serie
The problem is the queue is suspended before clearing address watch call
in KFD, there is not queue preemption and queue resume after clearing
call, and the test ends. So there is not chance to send MAP_PROCESS to
HWS. At this point FW has nothing to do. We have several test FWs from
Tej, none
[AMD Official Use Only - General]
This is a strange solution because the MEC should set watch controls as
non-valid automatically on queue preemption to avoid this kind of issue in the
first place by design. MAP_PROCESS on resume will take whatever the driver
requests.
GFX11 has no issue with
Yes. I will send out the fix for gc v9.4.3 later. Thanks for your review.
Eric
On 2023-08-10 17:02, Felix Kuehling wrote:
I think amdgpu_amdkfd_gc_9_4_3.c needs a similar fix. But maybe a bit
different because it needs to support multiple XCCs.
That said, this patch is
Reviewed-by: Felix Kue
I think amdgpu_amdkfd_gc_9_4_3.c needs a similar fix. But maybe a bit
different because it needs to support multiple XCCs.
That said, this patch is
Reviewed-by: Felix Kuehling
On 2023-08-10 16:47, Eric Huang wrote:
KFD currently relies on MEC FW to clear tcp watch control
register by sendin
KFD currently relies on MEC FW to clear tcp watch control
register by sending MAP_PROCESS packet with 0 of field
tcp_watch_cntl to HWS, but if the queue is suspended, the
packet will not be sent and the previous value will be
left on the register, that will affect the following apps.
So the solutio
On 2023-08-10 15:03, Jonathan Kim wrote:
Remove redundant assignment when skipping process ctx clear.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
Ping?
On Thu, Jul 27, 2023 at 2:11 PM Alex Deucher wrote:
>
> This patch set adds support for an application to query GPU
> page faults. It's useful for debugging and there are
> vulkan extensions that could make use of this. Preliminary
> user space code which uses this can be found here:
> ht
Even if there's nothing currently parsing amdgpu's coredump files, if
we eventually have such tools they will be glad to find a version field
to properly read the file.
Create a version number to be displayed on top of coredump file, to be
incremented when the file format or content get changed.
Giving that we use codedump just for device resets, move it's functions
and structs to a more semantic file, the amdgpu_reset.{c, h}.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 9 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 80 --
driv
Instead of storing coredump information inside amdgpu_device struct,
move if to a proper separated struct and allocate it dynamically. This
will make it easier to further expand the logged information.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 14 +++--
driver
During a GPU reset, a normal memory reclaim could block to reclaim
memory. Giving that coredump is a best effort mechanism, it shouldn't
disturb the reset path. Change its memory allocation flag to a
nonblocking one.
Signed-off-by: André Almeida
Reviewed-by: Christian König
---
drivers/gpu/drm/
Create a module parameter to disable soft recoveries on amdgpu, making
every recovery go through the device reset path. This option makes
easier to force device resets for testing and debugging purposes.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu
Hi,
The goal of this patchset is to improve debugging device resets on amdgpu.
The first patch creates a new module parameter to disable soft recoveries,
ensuring every recovery go through the full device reset, making easier to
generate resets from userspace tools like [0] and [1]. This is impor
Remove redundant assignment when skipping process ctx clear.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_que
On 8/10/2023 8:41 PM, Christian König wrote:
Am 10.08.23 um 13:44 schrieb Lijo Lazar:
Instead of maintaining a list per device, keep the reset handlers common
per ASIC family. A pointer to the list of handlers is maintained in
reset control.
Why should this be beneficial?
There is a global
No functional change. Use ratelimited version of pr_ to avoid
overflowing of dmesg buffer
Signed-off-by: Harish Kasiviswanathan
---
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c | 6 +++---
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c | 6 +++---
drivers/gpu/drm/amd/amdkfd/kfd_int_process
From: Joshua Ashton
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 32 +--
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +-
include/uapi/drm/drm_mode.h | 8 +
3 files changed, 38 insertion
Map the plane CTM driver-specific property to DC plane, instead of DC
stream. The remaining steps to program DPP block are already implemented
on DC shared-code.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 2
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
conflits with DRM CRTC CTM property.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgp
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
v2:
- remove redundant color caps assignment on plane degamma map (Harry)
- pass color caps to degamma params
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
dc->caps.color.mpc.gamut_remap says there is a post-blending color block
for gamut remap matrix for DCN3 HW family and newer versions. However,
those drivers still follow DCN10 programming that remap stream
gamut_remap_matrix to DPP (pre-blending).
To enable pre-blending and post-blending gamut_re
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_
Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD
display HW, 3D LUT comes after a shaper curve and we always have to
program a shaper curve to delinearize or normalize the color space
before applying a 3D LUT (since we have a reduced number of LUT
entries).
In this version, th
From: Joshua Ashton
Map plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
modu
Map DC shaper LUT to DM plane color management. Shaper LUT can be used
to delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. If a plane degamma is
apply to linearize the color space, a custom shaper 1D LUT can be used
just before applying
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Reviewed-by: Harry Wentland
Enable usage of predefined transfer func in addition to shaper 1D LUT.
That means we can save some complexity by just setting a predefined
curve, instead of programming a custom curve when preparing color space
for applying 3D LUT.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
drivers/gpu/drm/amd/display/i
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgp
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinat
From: Joshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority. That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We retu
DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.
Reviewed-by: Harry Wentland
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/dr
From: Joshua Ashton
We should reset a plane state if at least one of the color management
properties differs from old and new state.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amd
From: Joshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgp
From: Joshua Ashton
Add predefined transfer function programming. There is no pre-blending
out gamma ROM, but we can use AMD color modules to program LUT
parameters from a pre-defined TF and an empty regamma LUT (or bump up
LUT parameters with pre-defined TF setup).
v2:
- update crtc color mgmt
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D LUT
From: Joshua Ashton
Blend 1D LUT or a pre-defined transfer function can be set to linearize
content before blending, so that it's positioned just before blending
planes in the AMD color mgmt pipeline, and after 3D LUT (non-linear
space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Dri
Add AMD pre-defined transfer function property to default DRM CRTC
gamma to convert to wire encoding with or without a user gamma LUT.
v2:
- enable CRTC prop in the end of driver-specific prop sequence
- define inverse EOTFs as supported regamma TFs
- reword driver-specific function doc to remove
Add 3D LUT property for plane gamma correction using a 3D lookup table.
Since a 3D LUT has a limited number of entries in each dimension we want
to use them in an optimal fashion. This means using the 3D LUT in a
colorspace that is optimized for human vision, such as sRGB, PQ, or
another non-linear
On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT. Add pre-defined transfer function to enable delinearizing content
with or without shaper LUT, where AMD color module calculates the
resulted shaper curve. W
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR content,
Instead of relying on color block names to get the transfer function
intention regarding encoding pixel's luminance, define supported
Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that
includes pure gamma or standardized transfer functions.
Suggested-by: Harry Wentland
Signed-off-
Brief documentation about pre-defined transfer function usage on AMD
display driver and standardized EOTFs and inverse EOTFs.
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 39 +++
1 f
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to delinearize
content with or without LUT.
v2:
- rename TF enum prefix from DRM_ to AMDGPU_ (Harry)
- remove HLG TF
Signed-off-by: Joshua Ashton
Co-deve
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Reviewed-by: Harry
Hook up driver-specific atomic operations for managing AMD color
properties. Create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`.
First add plane degamma LUT properties that means user-blob and its
size. We will add
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Reviewed-by: Harry Wentland
Reviewed-by: Liviu Dudau
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
driv
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
-
Hi all,
Here is the next version of our work to enable AMD driver-specific color
management properties [1][2]. This series is a collection of
contributions from Joshua, Harry, and me to enhance the AMD KMS color
pipeline for Steam Deck/SteamOS by exposing additional pre-blending and
post-blending
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to 256 elements we can
define a better segment distribution for near-linear LUTs
for our maximum of 256 HW-supported point
On 8/10/23 00:37, Evan Quan wrote:
> diff --git a/Documentation/admin-guide/kernel-parameters.txt
> b/Documentation/admin-guide/kernel-parameters.txt
> index a1457995fd41..21f73a0bbd0b 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parame
Ping?
On Wed, Aug 9, 2023 at 3:10 PM Alex Deucher wrote:
>
> We need the domains in amdgpu_drm.h for the kernel driver to manage
> the pool, but we don't want userspace using it until the code
> is ready. So reject for now.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amd
Am 10.08.23 um 13:44 schrieb Lijo Lazar:
Instead of maintaining a list per device, keep the reset handlers common
per ASIC family. A pointer to the list of handlers is maintained in
reset control.
Why should this be beneficial?
Christian.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd
On 8/10/2023 12:37 AM, Evan Quan wrote:
The newly added WBRF feature needs this interface for channel
width calculation.
Signed-off-by: Evan Quan
---
include/net/cfg80211.h | 8
net/wireless/chan.c| 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/n
[AMD Official Use Only - General]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Thursday, August 10, 2023 6:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Kamal, Asad ; Zhang, Hawking
Subject: [PAT
On Thu, 10 Aug 2023 05:35:02 -0400, "Valdis KlÄtnieks" said:
> I am seeing the following consistent crash at boot:
> Some quick digging indicates the most likely culprit is:
>
> commit cbd0606e6a776bf2ba10d4a6957bb7628c0da947
> Author: Srinivasan Shanmugam
> Date: Thu Jul 20 15:39:24 2023 +05
Hello,
On 8/10/23 01:13, Maxime Ripard wrote:
> Hi,
>
> On Tue, Aug 08, 2023 at 11:02:45AM -0700, Nikita Zhandarovich wrote:
>> Four hdmi_*_infoframe_init() functions that initialize different
>> types of hdmi infoframes only return the default 0 value, contrary to
>> their descriptions. Yet thes
Remove duplicated includes in amdgpu_amdkfd_gpuvm.c and amdgpu_ttm.c.
Resolves checkincludes message.
Signed-off-by: GUO Zihua
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers
I am seeing the following consistent crash at boot:
[ 61.211213][ T819] [drm] radeon kernel modesetting enabled.
[ 61.584870][ T819] vga_switcheroo: detected switching method
\_SB_.PCI0.GFX0.ATPX handle
[ 61.667507][ T819] ATPX version 1, functions 0x0033
[ 61.748228][ T819] gener
Instead of maintaining a list per device, keep the reset handlers common
per ASIC family. A pointer to the list of handlers is maintained in
reset control.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/aldebaran.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.
Temperature needs to be reported in millidegree Celsius.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
b/drivers/gpu/drm/amd/pm/
[AMD Official Use Only - General]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Thursday, August 10, 2023 4:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice
Subject: [PATCH] drm/amdgpu: Add I2C EEPROM support on smu v1
Support I2C EEPROM on smu v13_0_6.
v2: Move IP_VERSION(13, 0, 6) ahead of IP_VERSION(13, 0, 10).
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/a
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Asad
> Kamal
> Sent: Wednesday, August 9, 2023 5:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Lazar, Lijo ; Kamal, Asad ;
> Zhang, Hawking
> Subject: [PATCH] drm/amd/pm: Add vclk and dclk sysnode for GC 9.4.3
>
> Expose sysfs
Support I2C EEPROM on smu v13_0_6.
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 4287743e121245..27fb9b64001
Hi,
On Tue, Aug 08, 2023 at 11:02:45AM -0700, Nikita Zhandarovich wrote:
> Four hdmi_*_infoframe_init() functions that initialize different
> types of hdmi infoframes only return the default 0 value, contrary to
> their descriptions. Yet these functions are still unnecessarily checked
> against po
Fulfill the SMU13.0.7 support for Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
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