[AMD Official Use Only - General]
Reviewed-by: Feifei Xu
-Original Message-
From: lyndonli
Sent: Monday, April 24, 2023 9:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun ; Zhao, Victor ;
Feng, Kenneth ; Xu, Feifei ; Li,
Yunxiang (Teddy) ; Li, Lyndon
Subject: [PATCH 1/2] d
[AMD Official Use Only - General]
I think you might be refer to : mod parameter reset_method will not affect the
loading driver code path. If loading driver, it should use the default reset
which might be mode1/mode2 or BACO instead of the specific mode2.
With the confusing commit msg corrected
Hi André,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.3 next-20230421]
[If
Below call trace and errors are observed when reloading
amdgpu driver with the module parameter reset_method=3.
It should do a mode1 reset when loading the driver.
[ +2.180243] [drm] psp gfx command ID_LOAD_TOC(0x20) failed
and response status is (0x0)
[ +0.11] [drm:psp_hw_start [amdgpu]] *
Before this change, sienna_cichlid_get_reset_handler will always
return NULL, although the module parameter reset_method is 3
when loading amdgpu driver.
Signed-off-by: lyndonli
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 +-
1 file changed, 1 insertion(+), 1
When a DRM job timeout, the GPU is probably hang and amdgpu have some
ways to deal with that, ranging from soft recoveries to full device
reset. Anyway, when userspace ask the kernel the state of the context
(via AMDGPU_CTX_OP_QUERY_STATE), the kernel reports that the device was
reset, regardless i
On Tue Apr 18, 2023 at 6:49 PM EEST, Lorenzo Stoakes wrote:
> No invocation of get_user_pages() uses the vmas parameter, so remove
> it.
>
> The GUP API is confusing and caveated. Recent changes have done much to
> improve that, however there is more we can do. Exporting vmas is a prime
> target as
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
Signed-off-by: Joshua Ashton
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 34 ---
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/dr
As per previous code, copy shaper, 3d and blend settings from dc_plane
to surface_updates before commit.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/a
From: Joshua Ashton
Map DRM plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Signed-off-by: Joshua Ashton
We already have the steps to program post-blending shaper/3D LUT on AMD
display driver, so that we can reuse them and map plane properties to DC
plane for pre-blending (plane) shaper/3D LUT setup.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 34 +
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 3 +++
2 files changed, 4 insertions(+)
d
DC only has pre-blending degamma caps (pre-blending/DPP) that is
currently in use for CRTC/post-blending degamma, so that we don't have
HW caps to perform plane and CRTC degamma at the same time. Reject
atomic updates when serspace sets both plane and CRTC degamma
properties.
Signed-off-by: Meliss
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Signed-off-by: Joshua Ashton
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
drivers/gpu/drm/amd/display/include/fixed31_32.h | 12
2 files change
From: Joshua Ashton
We only set CRTC degamma if we don't have plane degamma LUT or TF to
configure. We return -EINVAL if we don't have plane degamma settings, so
we can continue and check CRTC degamma.
Signed-off-by: Joshua Ashton
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
.../
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinat
We took a similar path for CRTC color mgmt changes, since we remap CRTC
degamma to plane/DPP block. Here we can use the status of
`plane->color_mgmt_changed` to detect when a plane color property
changed and recreate the plane accordingly.
Co-developed-by: Joshua Ashton
Signed-off-by: Joshua Asht
Inspired by regamma TF, follow similar steps to add TF + 1D LUT for
shaper func. Reuse gamma_tf property, since the driver doesn't support
shaper and out gamma at the same time. We could rename gamma_tf, if
necessary to avoid misunderstandings, or add a specific property for
shaper lut.
Signed-off
Now, we can use DRM CRTC shaper LUT to delinearize and/or normalize the
color space for a more efficient 3D LUT support (so far, only for DRM
atomic color mgmt). If a degamma 1D LUT is passed to linearize the color
space, a custom shaper 1D LUT can be used before applying 3D LUT.
NOTE: although DR
From: Joshua Ashton
Otherwise this is just initialized to 0.
This needs to actually have a value so that compute_curve can work
for PQ EOTF.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
From: Joshua Ashton
Add predefined transfer function programming. There is no out gamma ROM,
but we can use AMD color modules to program LUT parameters from a
predefined TF and an empty regamma LUT (or power LUT parameters with
predefined TF setup).
Signed-off-by: Joshua Ashton
---
.../amd/dis
Map DRM CRTC 3D LUT in the atomic color mgmt pipeline to DC
(post-blending). 3D LUT works better in a non-linear color space,
therefore using a degamma to linearize the input space may produce
unexpected results. The next patch introduces shaper LUT support that
can be used to delinearize the color
Decouple steps of post-blending shaper LUT setup and LUT size validation
according to HW caps as a preparation for DRM CRTC shaper LUT support.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 67 ---
1 file changed, 58 insertions(+), 9 deletions(-)
From: Joshua Ashton
dc_acquire_release_mpc_3dlut_for_ctx initializes the bits required to
program 3DLUT in DC MPC hw block, applied in set_output_transfer_func().
Since acquire/release can fail, we should check resources availability
during atomic check considering the new context created. We dyn
In the original dc_acquire_release_mpc_3dlut(), only current ctx is
considered, which doesn't fit the steps for atomic checking new ctx.
Therefore, create a function to handle 3D LUT resource for a given
context, so that we can check resources availability in atomic_check
time and handle failures p
HW allows us to program shaper LUT without 3D LUT settings and it is
also good for testing shaper LUT behavior, therefore, DC driver should
allow acquiring both 3D and shaper LUT, but programing shaper LUT
without 3D LUT (not initialized).
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/displ
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed
We are introducing DRM 3D LUT property to DM color pipeline in the next
patch, but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce
It follows the same path of out_transfer_func for stream updates, since
shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func()
and this function is called in the atomic commit_tail when
update_flags.bits.out_tf is set.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/d
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/dr
From: Joshua Ashton
Blend 1D LUT or a predefined transfer function can be set to linearize
content before blending, so that it's positioned just before blending
planes, and after 3D LUT (non-linear space). Shaper and Blend LUTs are
1D LUTs that sandwich 3D LUT. Drivers should advertize blend prop
Add property to set predefined transfer function to enable delinearizing
content with or without shaper LUT. Drivers should advertize this
property acoording to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +
drivers/gpu/drm/amd/amdgp
Add 3D LUT property for plane gamma correction using a 3D lookup table.
3D LUT is more effective when applying in non-linear space, therefore,
userpace may need one 1D LUT (shaper) before it to delinearize content
and another 1D LUT after 3D LUT (blend) to linearize content again for
blending. The
Shaper 1D LUT delinearizes content before applying 3D LUT so that, it
comes before 3D LUT. It's an optional property and drivers should attach
it according to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amd
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR content,
From: Joshua Ashton
Create driver-private properties (not DRM KMS generic) for plane degamma
LUT (user-blob and its size).
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14
drivers/gpu/drm/amd/amd
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to delinearize
content with or without LUT (using hardcoded curve caps).
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |
>From amdgpu_dm_plane we can get it for both CRTC and plane color
properties. We are adding new plane properties for AMD driver-private
color mgmt.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 37 +--
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c
From: Joshua Ashton
Add predefined transfer function property to DRM CRTC gamma to convert
to wire encoding with or without gamma LUT.
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 22 +
We will add color mgmt properties to DRM planes in the text patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Signed-off-by: Mel
In the next patches we are adding 17 new properties for color
correction:
- CRTC: 3D LUT+size, shaper LUT+size, regamma TF (5)
- Plane: Degamma LUT+size+TF, HDR multiplier, shaper LUT+size+TF, 3D LUT+size,
blend
LUT+size+TF (12)
We still need to detach driver-private counter from DRM/KMS-generic
Add CRTC 3D LUT for gamma correction using a 3D lookup table. A shaper
lut must be set to shape the content for a non-linear space. That
details should be handled by the driver according to HW color
capabilities.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +
CRTC shaper LUT shapes the content after blending, i.e., de-linearizes
or normalizes space before applying a 3D LUT color correction. In the
next patch, we add CRTC 3D LUT property to DRM color management after
this shaper LUT and before the current CRTC gamma LUT.
Signed-off-by: Melissa Wen
---
We are enabling a large set of color calibration features to enhance KMS
color mgmt but these properties are specific of AMD display HW, and
cannot be provided by other vendors. Therefore, set a config option to
enable AMD driver-private properties used on Steam Deck color mgmt
pipeline.
Co-develo
From: Harry Wentland
The shaper LUT requires a 10-bit value of the delta between
segments. We were using dc_fixpt_clamp_u0d10() to do that
but it doesn't do what we want it to do. It will preserve
10-bit precision after the decimal point, but that's not
quite what we want. We want 14-bit precisio
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to 256 elements we can
define a better segment distribution for near-linear LUTs
for our maximum of 256 HW-supported point
Hi all,
Joshua Ashton and I (with the great collaboration of Harry Wentland -
thanks) have been working on KMS color pipeline enhancement for Steam
Deck/SteamOS by exposing the large set of color caps available in AMD
display HW.
This patchset results from this full-stack work, including pre-blen
Hi Alex,
We might want to move the mes_v11_0's mqd to VRAM, too. According to my test
result, moving mes queue's mqd to vram will lead to better performance than
only moving gfx&compute queues' mqd.
Regards & Thanks,
Yubiao
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Se
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