tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 31bd35b66249699343d2416658f57e97314a433a Add linux-next specific
files for 20230403
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303082135.njdx1bij-...@intel.com
https
On 4/3/23 20:54, Christian König wrote:
Am 03.04.23 um 21:40 schrieb Joshua Ashton:
Hello all!
I would like to propose a new API for allowing processes to control
the priority of GPU queues similar to RLIMIT_NICE/RLIMIT_RTPRIO.
The main reason for this is for compositors such as Gamescope a
On GFX11, CP_HQD_HQ_STATUS0[29] bit will be used by CPFW to acknowledge
whether PCIe atomics are supported. The default value of this bit is set
to 0. Driver will check whether PCIe atomics are supported and set the
bit to 1 if supported. This will force CPFW to use real atomic ops.
If the bit is n
Am 03.04.23 um 21:40 schrieb Joshua Ashton:
Hello all!
I would like to propose a new API for allowing processes to control
the priority of GPU queues similar to RLIMIT_NICE/RLIMIT_RTPRIO.
The main reason for this is for compositors such as Gamescope and
SteamVR vrcompositor to be able to create
Am 03.04.23 um 21:40 schrieb Joshua Ashton:
This allows AMDGPU scheduler priority above normal to be expressed
using the DRM_SCHED_PRIORITY enum.
That was rejected before, I just don't remember why exactly. Need to dig
that up again.
Christian.
Signed-off-by: Joshua Ashton
---
drivers/
Add support for the new RLIMIT_GPUPRIO when doing the priority
checks creating an amdgpu_ctx.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/driver
Introduce a new RLIMIT that allows the user to set a runtime limit on
the GPU scheduler priority for tasks.
This avoids the need for leased compositors such as SteamVR's
vrcompositor to be launched via a setcap'ed executable with
CAP_SYS_NICE.
This is required for SteamVR as it doesn't run as a D
This allows AMDGPU scheduler priority above normal to be expressed
using the DRM_SCHED_PRIORITY enum.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
include/drm/gpu_scheduler.h | 1 +
3 files changed, 3
This allows it to be used by other parts of the codebase without fear
of a circular include dependency being introduced.
Signed-off-by: Joshua Ashton
---
include/drm/drm_sched_priority.h | 41
include/drm/gpu_scheduler.h | 15 +---
2 files changed, 4
Hello all!
I would like to propose a new API for allowing processes to control
the priority of GPU queues similar to RLIMIT_NICE/RLIMIT_RTPRIO.
The main reason for this is for compositors such as Gamescope and
SteamVR vrcompositor to be able to create realtime async compute
queues on AMD without
dmabuf is allocated/mapped as GTT domain, when dma-unmapping dmabuf
changing placement to CPU will trigger memory eviction after calling
ttm_bo_validate, and the eviction will cause performance drop.
Keeping the correct domain will solve the issue.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/a
This patch is,
Reviewed-by: Luben Tuikov
Regards,
Luben
On 2023-03-31 15:54, Alex Deucher wrote:
> All chips that support RAS also support IP discovery, so
> use the IP versions rather than a mix of IP versions and
> asic types. Checking the validity of the atom_ctx pointer
> is not required a
On 2023-03-31 15:30, Alex Deucher wrote:
> On Tue, Mar 28, 2023 at 12:30 PM Luben Tuikov wrote:
>>
>> On 2023-03-27 20:11, Alex Deucher wrote:
>>> All chips that support RAS also support IP discovery, so
>>> use the IP versions rather than a mix of IP versions and
>>> asic types.
>>>
>>> Signed-of
On 4/2/23 18:08, Mario Limonciello wrote:
> The array is hardcoded to 8 in atomfirmware.h, but firmware provides
> a bigger one sometimes. Deferencing the larger array causes an out
> of bounds error.
>
> commit 4fc1ba4aa589 ("drm/amd/display: fix array index out of bound error
> in bios parser")
[Public]
Hi all,
This week this patchset was tested on the following systems:
Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
Lenovo Thinkpad T13s Gen4 with AMD Ryzen 5 6600U
Reference AMD RX6800
These systems were tested on the following display types:
eDP, (1080p 60hz [5650U]) (1920x12
[AMD Official Use Only - General]
Reviewed-By: Horace Chen
-Original Message-
From: Yifan Zha
Sent: Monday, April 3, 2023 3:35 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Chen, Horace ; Zhang, Hawking
; Chang, HaiJun
Cc: Zha, YiFan(Even)
Subject: [PATCH v2 2/2] drm/am
On Fri, Mar 31, 2023 at 06:19:55PM -0400, Alex Deucher wrote:
> Hi Dave, Daniel,
>
> More new stuff for 6.4.
>
> The following changes since commit d36d68fd1925d33066d52468b7c7c6aca6521248:
>
> Merge tag 'drm-habanalabs-next-2023-03-20' of
> https://git.kernel.org/pub/scm/linux/kernel/git/oga
[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive
[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver
v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS
Signed-off-by: Yifan Zha
---
[AMD Official Use Only - General]
OK, Will do.
-
Best Regards,
Thomas
-Original Message-
From: Zhou1, Tao
Sent: Monday, April 3, 2023 3:21 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Li, Candice ;
Yang, Stanley
Subject: RE: [PATCH 1/2] dr
[AMD Official Use Only - General]
> -Original Message-
> From: Chai, Thomas
> Sent: Monday, April 3, 2023 3:00 PM
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Li, Candice
> ; Yang, Stanley
> Subject: RE: [PATCH 1/2] drm/amdgpu: optimize redundant code in umc_
[AMD Official Use Only - General]
-
Best Regards,
Thomas
-Original Message-
From: Zhou1, Tao
Sent: Monday, April 3, 2023 11:45 AM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Li, Candice ;
Yang, Stanley
Subject: RE: [PATCH 1/2] drm/amdgpu: o
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