[AMD Official Use Only - General]
Hi Tim.
> -Original Message-
> From: Huang, Tim
> Sent: Thursday, March 30, 2023 10:33 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Limonciello, Mario
> ; Zhang, Yifan ;
> Yuan, Perry ; Du, Xiaojian ;
> Ma, Li ; Huang, Tim
> Subject
Am 29.03.23 um 17:25 schrieb Alex Deucher:
Use the new callback to fetch the data. Return an error if
not supported. UMDs should use this query to check whether
shadow buffers are supported and if so what size they
should be.
v2: return an error rather than a zerod structure.
v3: drop GDS,
Am 29.03.23 um 17:25 schrieb Alex Deucher:
Used to get the size and alignment requirements for
the gfx shadow buffer for preemption.
v2: use FW version check to determine whether to
return a valid size here
return an error if not supported (Alex)
v3: drop GDS (Alex)
Signed-off-by: Ale
Am 29.03.23 um 17:25 schrieb Alex Deucher:
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
driv
Am 29.03.23 um 17:25 schrieb Alex Deucher:
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on fir
On 29/03/2023 21:46, Alex Deucher wrote:
On Wed, Mar 29, 2023 at 3:21 PM Shashank Sharma wrote:
Hey Alex,
On 29/03/2023 19:57, Alex Deucher wrote:
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue.
Am 29.03.23 um 17:25 schrieb Alex Deucher:
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMD
On 3/29/23 22:36, Kai-Heng Feng wrote:
On Wed, Mar 29, 2023 at 9:23 PM Mario Limonciello
wrote:
On 3/29/23 04:59, Kai-Heng Feng wrote:
When the power is lost due to ACPI power resources being turned off, the
driver should reset the GPU so it can work anew.
First, _PR3 support of the hierar
[AMD Official Use Only - General]
Please update the patch headers for the series with the prefix "drm/amd/pm" to
align with other power changes.
With that fixed, the series is reviewed-by: Evan Quan
Evan
> -Original Message-
> From: Tong Liu01
> Sent: Thursday, March 30, 2023 11:15 AM
Enable node pp_dpm_vclk1 and pp_dpm_dclk1 for gc11.0.2 and gc11.0.3
Signed-off-by: Tong Liu01
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index d8b9c613
Enable vclk1 and dclk1 node for gc10.3.0 and gc10.3.1
Signed-off-by: Tong Liu01
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ced295eeaf97..d8b9c6136fc0 100644
---
User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of
vcn and dcn
Signed-off-by: Tong Liu01
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 2 ++
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 32 +++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 +
3 f
Skip mode2 reset only for IMU enabled APUs when do S4.
This patch is to fix the regression issue
https://gitlab.freedesktop.org/drm/amd/-/issues/2483
It is generated by patch "2bedd3f21b30 drm/amdgpu: skip ASIC reset
for APUs when go to S4".
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdg
On Wed, Mar 29, 2023 at 8:49 PM Kai-Heng Feng
wrote:
>
> On Wed, Mar 29, 2023 at 9:21 PM Alex Deucher wrote:
> >
> > On Wed, Mar 29, 2023 at 6:00 AM Kai-Heng Feng
> > wrote:
> > >
> > > When the power is lost due to ACPI power resources being turned off, the
> > > driver should reset the GPU so
[AMD Official Use Only - General]
> -Original Message-
> From: Tong Liu01
> Sent: Wednesday, March 29, 2023 6:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Chen, Horace
> ; Tuikov, Luben ;
> Koenig, Christian ; Deucher, Alexander
> ; Xiao, Jack ; Zhang,
> Hawking ; Liu, M
On Wed, Mar 29, 2023 at 9:21 PM Alex Deucher wrote:
>
> On Wed, Mar 29, 2023 at 6:00 AM Kai-Heng Feng
> wrote:
> >
> > When the power is lost due to ACPI power resources being turned off, the
> > driver should reset the GPU so it can work anew.
> >
> > First, _PR3 support of the hierarchy needs t
Hi Dave, Daniel,
Fixes for 6.3.
The following changes since commit 197b6b60ae7bc51dd0814953c562833143b292aa:
Linux 6.3-rc4 (2023-03-26 14:40:20 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.3-2023-03-29
for you to fetch
Applied. Thanks!
On Wed, Mar 29, 2023 at 1:31 AM Zhang, Hawking wrote:
>
> [AMD Official Use Only - General]
>
> Reviewed-by: Hawking Zhang
>
> Regards,
> Hawking
> -Original Message-
> From: Dan Carpenter
> Sent: Wednesday, March 29, 2023 13:28
> To: Zhang, Hawking
> Cc: Koenig, Chri
From: Hawking Zhang
Add smuio v13_0_3 register offset and shift masks
header files
v2: update headers (Alex)
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
.../asic_reg/smuio/smuio_13_0_3_offset.h | 177
.../asic_reg/smuio/smuio_13_0_3_sh_mask.
From: Rajneesh Bhardwaj
Add smuio v13_0_3 callbacks for SMUIO.
Tested-by: Ori Messinger
Acked-by: Alex Deucher
Reviewed-by: Lijo Lazar
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.
From: Hawking Zhang
Add callbacks for SMUIO 13.0.3
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4
drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/driv
This add support for the SMUIO 13.0.3 block.
Hawking Zhang (2):
drm/amdgpu: add smuio v13_0_3 ip headers
drm/amdgpu: init smuio funcs for smuio v13_0_3
Rajneesh Bhardwaj (1):
drm/amdgpu: implement smuio v13_0_3 callbacks
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/d
From: Le Ma
Number of instances is extended.
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
From: Hawking Zhang
it is used for user space driver to identify gfx_v9_4_3 chip
Signed-off-by: Hawking Zhang
Acked-by: Alex Deucher
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/
From: Lijo Lazar
Add programming of SDMA golden settings for v4.4.2
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers
From: Lijo Lazar
IH follows a different identification scheme for its clients. Get the
right mapping of xcc instance from IH node id.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 35 +
1 file ch
From: Tom St Denis
This patch updates the 'regs2' interface for MMIO
registers to add a new IOCTL command for a 'v2' state
data that includes the XCC ID.
This patch then updates amdgpu_gfx_select_se_sh()
and amdgpu_gfx_select_me_pipe_q() (and the implementations
in the gfx drivers) to support an
From: Le Ma
Use WREG32_SOC15_EXT to write registers with address larger than 32bit.
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 45 +++---
1 file changed, 12 insertions(+), 33 deletions(-)
diff --g
From: Hawking Zhang
gfx v9_4_3 only support compute. render backend
doesn't need to be involved in any compute shader
execution.
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 44 -
1 file chan
From: Le Ma
Truncate the 64bit base address from ip discovery and only store lower 32bit
ip base in reg_offset[].
Bits > 32 follows ASIC specific format, thus just discard them and handle it
within specific ASIC.
By this way reg_offset[] and related helpers can stay unchanged.
v2: make comment
From: Le Ma
version 4 supports 64bit ip base address
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 42 +--
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Le Ma
version 4 supports 64bit ip base address
Signed-off-by: Le Ma
Signed-off-by: Hawking Zhang
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/discovery.h | 30 -
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git
From: Le Ma
SMN address which is larger than 32bit has different indications
through bit[34:32] on different AIDs.
v2: put smn addressing of different AIDs into asic specific place
v3: change to ext_id/ext_offset naming
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
From: Le Ma
Use WREG_SOC15x() instead of WREG32(SOC15_REG_OFFSET())
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Le Ma
New ip_discovery binary size is increased.
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
From: Le Ma
New doorbell index assignment is used by aqua_vanjaram.
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +++-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
2 files changed, 24 insertions(+), 1 d
From: Le Ma
New doorbell index assignment is used by aqua_vanjaram.
Signed-off-by: Le Ma
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +++-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
2 files changed, 24 insertions(+), 1 d
From: Lijo Lazar
Add a mask of SDMA instances available for use. On certain ASIC configs,
not all SDMA instances are available for software use.
v2:
Change sdma mask type to uint32_t (Le)
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deuc
From: Lijo Lazar
For aqua vanjaram, add mapping for logical to physical
instances.
v2:
Register accesses on bare metal should be based on physical
instance. Use GET_INST() to get physical instance.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by:
From: Lijo Lazar
Add XCC logical to physical instance map for aqua vanjaram
v2:
Keep look up table only for required IPs, for others return
default mapping (Felix).
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Felix Kuehling
Signed-off-by: Ale
From: Le Ma
Four basic reasons as below to do the change:
1. number of ring expand a lot on aqua_vanjaram, and adjustment on old
assignment cannot make each ring in a continuous doorbell space.
2. the SDMA doorbell index should not exceed 0x1FF on aqua_vanjaram due to
regDOORBELLx_C
From: Lijo Lazar
In GC v9.4.3 there are multiple XCCs. It's required to use
physical instance number to get the right register offset. Use
GET_INST API for that.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +
From: Lijo Lazar
On initialization set the partition mode correctly to SPX (default) or
any other user specified partition mode. Use switch_compute_partition
API so that all settings are initialized correctly.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
--
From: Le Ma
Use s2a entry 5/6 registers to decode sdma doorbell trans on different AIDs,
which aligns the entry table in SHUB spec, and leave entry 4 dedicated for VCN
doorbell to avoid conflict.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/
From: Mukul Joshi
For GFX 9.4.3, use the logical to physical mapping table,
to get the correct XCD instance when accessing registers on
bare metal.
Signed-off-by: Mukul Joshi
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 5 +-
.../gpu
From: Mukul Joshi
Fix the if condition which causes dynamic repartitioning
to fail when trying to switch to DPX mode.
Signed-off-by: Mukul Joshi
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +-
1 file changed, 5 insertions(+), 1 delet
From: Mukul Joshi
The recent overhauling of SDMA queue management introduced a
bug where XGMI SDMA user-mode queue allocation would mark bits
in the SDMA queue bitmap as set, representing a queue from
non-XGMI SDMA engines was allocated. This patch
addresses this issue and fixes the xGMI SDMA que
From: Mukul Joshi
Update interrupt handling in CPX mode for GFX9.4.3 by using the
VMID space instead of SDMA client id to determine if an interrupt
should be processed by a KFD node. This is especially needed for
handling retry faults from MMHUB.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Ku
From: Shiwu Zhang
Since extended data is not supported, num_links should
be accumulated to reflect the xgmi topology info.
Signed-off-by: Shiwu Zhang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
1 file changed, 2 insertions(+),
From: Amber Lin
GFX_9_4_3 supports multi-XCDs and multi-AIDs in one GPU device. SWS needs
to program IH_VMID_x_LUT with specified XCC instance and corresponded
AID instance.
Signed-off-by: Amber Lin
Reviewed-by: Mukul Joshi
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_
From: Mukul Joshi
On GFX 9.4.3, there can be multiple KFD nodes. As a result,
SMI events for SVM, queue evict/restore should be raised for
each node independently.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
From: Le Ma
It's not required for compute pipeline and will cause soft lockup on emulation
due to long-time writing.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 99 -
1 file changed, 99 dele
From: Alex Sierra
This work is required for GC 9.4.3, previous to support memory
partitions per node at SVM. When multiple partition is configured,
every BO should be allocated inside one specific partition which
corresponds to the current amdgpu_device and kfd_node.
v2: squash in compilation fi
From: Lijo Lazar
Program partition status register to reflect the current partition mode.
Partition capability register is for capability and is a one-time setting.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 2
From: Lijo Lazar
The packet expects only 16 bits register offset. Hence pass register
offset which is local to each XCC.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 ---
1 file changed, 4 insertions(+),
From: James Zhu
add vcn multiple AIDs support.
v2: squash in FW setting fix (Alex)
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 810 +---
1 file changed, 434 insertions(+), 376 deletions(-)
diff --g
From: James Zhu
Update clock gate setting.
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 30 +
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.
From: James Zhu
Add JPEG multiple AIDs support.
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 380 ++-
1 file changed, 227 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg
From: Lijo Lazar
For ASICs with sdma IP v4.4.2, add mapping for logical to physical
instances.
v2:
Register accesses on bare metal should be based on physical
instance. Use GET_INST() to get physical instance.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Si
From: Lijo Lazar
It needs to be done only for XCC instances in non-AID0. Use the physical
instance to determine non-AID0 XCC instances.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 9 ++---
1 file changed, 6 insert
From: Lijo Lazar
Add a map for logical to physical instances of an IP. For ex: on some device
configurations, the first logical XCC may not be the first physical XCC.
Software may continue to access in logical IP instance order. The map
provides a convenient way to get to the actual physical inst
From: James Zhu
Update vcn doorbell range to support multiple AIDs.
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h | 1 +
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 20 +---
2 files changed, 18 insertions(+
From: Lijo Lazar
Register accesses need to be based on physical instance on bare metal.
Pass the right instance using logical to physical instance lookup
table before accessing registers. Add a macro GET_INST to get the right
physical instance of an IP corresponding to a logical instance.
v2: fi
From: Le Ma
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access
nonAID0 register smn address and new PCI_INDEX_HI register is introduced
to access the higher bits.
v2: rebase on latest register accessors (Alex)
Signed-off-by: Le Ma
Acked-by: Felix Kuehling
Reviewed-by:
From: Mukul Joshi
GFX9.4.3 will support dynamic repartitioning of the GPU through sysfs.
Add device repartitioning support in KFD to repartition GPU from one
mode to other.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgp
From: Mukul Joshi
Currently, even if kfd_locked is set, a process is first
created and then removed to work around a race condition
in updating kfd_locked flag. Rework kfd_locked handling to
ensure no processes is created if kfd_locked is set. This
is achieved by updating kfd_locked under kfd_pro
From: Lijo Lazar
Add a mask of SDMA instances available for use. On certain ASIC configs,
not all SDMA instances are available for software use.
v2:
Change sdma mask type to uint32_t (Le)
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deuc
From: Le Ma
Configure the sdma doorbell settings on NBIF0 and SYSHUB of each AID
v2: fetch aid_id from amdgpu_sdma_instance (Lijo)
Signed-off-by: Le Ma
Acked-by: Felix Kuehling
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 65 +
From: Jonathan Kim
Similar to GFX9.4.2 non-A+A devices, GFX9.4.3 psp xgmi topology info is
half duplex and requires the driver to fill in the bidirectional info.
Signed-off-by: Jonathan Kim
Reviewed-by: Shiwu Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 11
From: David Belanger
On GC 9.4.3, we are removing the EOP buffer.
If we specify 0 for the size, CP_HQD_EOP_CONTROL ends up with
incorrect value as order_size_2 calculations does not handle 0.
Fix it by using zero for the MQD entry for EOP size 0.
v2: Reworked code with a conditional assignment
On Wed, Mar 29, 2023 at 3:21 PM Shashank Sharma wrote:
>
> Hey Alex,
>
> On 29/03/2023 19:57, Alex Deucher wrote:
> > On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
> > wrote:
> >> From: Alex Deucher
> >>
> >> This patch intorduces new UAPI/IOCTL for usermode graphics
> >> queue. The userspace
Hey Alex,
On 29/03/2023 19:57, Alex Deucher wrote:
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work qu
On 3/29/23 14:05, Caio Novais wrote:
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no
previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’
[-Wmissing-prototypes]
Get rid of it by marking the function as
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no
previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’
[-Wmissing-prototypes]
Get rid of it by marking the function as static
Signed-off-by: Caio Novais
---
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:
In function ‘dml_rq_dlg_get_dlg_params’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14:
warning: variable ‘scl_enable’ set but not u
This patchset removes one unused variable and mark a function as static.
Caio Novais (2):
drm/amd/display: Remove unused variable 'scl_enable'
drm/amd/display: Mark function
'optc3_wait_drr_doublebuffer_pending_clear' as static
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
>
> From: Alex Deucher
>
> This patch intorduces new UAPI/IOCTL for usermode graphics
> queue. The userspace app will fill this structure and request
> the graphics driver to add a graphics work queue for it. The
> output of this UAPI is a q
Am 29.03.23 um 18:04 schrieb Shashank Sharma:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
output of this UAPI is a queue id.
This UAPI ma
On 3/28/23 18:09, Caio Novais wrote:
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no
previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’
[-Wmissing-prototypes]
Get rid of it by adding a function prot
From: Arvind Yadav
This patch:
- adds some new parameters defined for the gfx usermode queues
use cases in the v11_mqd_struct.
- sets those parametes with the respective allocated gpu context
space addresses.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Signed-off-by: Arvind
From: Arvind Yadav
To support oversubscription, MES expects WPTR BOs to be mapped
to GART, before they are submitted to usermode queues.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 89
The userspace sends us the doorbell object and the doobell index
to be used for the usermode queue, but the FW expects the absolute
doorbell index on the PCI BAR in the MQD. This patch adds a function
to convert this relative doorbell index to the absolute doorbell index.
This patch is dependent o
From: Shashank Sharma
This patch adds new functions to map/unmap a usermode queue into
the FW, using the MES ring. As soon as this mapping is done, the
queue would be considered ready to accept the workload.
V1: Addressed review comments from Alex on the RFC patch series
- Map/Unmap should
From: Shashank Sharma
The FW expects us to allocate atleast one page as context space to
process gang, process, shadow, GDS and FW related work. This patch
creates a joint object for the same, and calculates GPU space offsets
for each of these spaces.
V1: Addressed review comments on RFC patch:
From: Shashank Sharma
A Memory queue descriptor (MQD) of a userqueue defines it in the harware's
context. As MQD format can vary between different graphics IPs, we need gfx
GEN specific handlers to create MQDs.
This patch:
- Introduces MQD hander functions for the usermode queues.
- Adds new fun
From: Shashank Sharma
This patch adds skeleton code for amdgpu usermode queue. It contains:
- A new files with init functions of usermode queues.
- A queue context manager in driver private data.
V1: Worked on design review comments from RFC patch series:
(https://patchwork.freedesktop.org/serie
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
output of this UAPI is a queue id.
This UAPI maps the queue into GPU, so the graphics app can s
From: Shashank Sharma
This patch adds:
- A new IOCTL function to create and destroy
- A new structure to keep all the user queue data in one place.
- A function to generate unique index for the queue.
V1: Worked on review comments from RFC patch series:
- Alex: Keep a list of queues, instead o
This patch series introduces AMDGPU usermode queues for gfx workloads.
Usermode queues is a method of GPU workload submission into the graphics
hardware without any interaction with kernel/DRM schedulers. In this
method, a userspace graphics application can create its own workqueue
and submit it di
On 3/28/23 18:09, Caio Novais wrote:
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:
In function ‘dml_rq_dlg_get_dlg_params’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14:
warni
This patch:
- adds a doorbell object in MES structure, to manage the MES
doorbell requirements in kernel.
- Removes the doorbell management code, and its variables from
the doorbell_init function, it will be done in doorbell manager
now.
- creates doorbell pages for MES kernel level needs (do
This patch:
- Adds a amdgpu_doorbell object in MES process.
- Allocs doorbell pages for MES process using doorbell manager.
- uses doorbell manager to get an absolute index of doorbells.
- removes a offset calculation function which is no more required.
- removes prototype of a few functions which
This patch removes some variables and functions from KFD
doorbell handling code, which are no more required since
doorbell manager is handling doorbell calculations.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 32
This patch:
- adds a new doorbell manager object in kfd pdd structure.
- allocates doorbells for a process while creating its pdd.
- frees the doorbells with pdd destroy.
- uses direct doorbell manager API for doorbell indexing.
- removes previous calls to allocate process doorbells as
its not re
This patch adds a helper function which converts a doorbell's
relative index in a BO to an absolute doorbell offset in the
doorbell BAR.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 15 +++
.../gpu/drm/amd/amdg
This patch:
- adds a doorbell manager structure in kfd device structure.
- plugs-in doorbell manager APIs for KFD kernel doorbell allocations
an free functions.
- removes the doorbell bitmap, uses the one into the doorbell manager
structure for all the allocations.
- updates the get_kernel_door
This patch:
- updates start/end values for each of the doorbell object
created.
- adds a function which validates that the kernel doorbell read/write
is within this range.
- uses this function during doorbell writes from kernel.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank S
From: Shashank Sharma
This patch adds helper functions to create and free doorbell
pages for kernel objects.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 41
.../gpu/drm/amd/amdgpu/amdgpu_doorbell_mg
From: Shashank Sharma
This patch initialzes the ttm resource manager for doorbells.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_t
From: Alex Deucher
This patch adds flags for a new gem domain AMDGPU_GEM_DOMAIN_DOORBELL
in the UAPI layer.
V2: Drop 'memory' from description (Christian)
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 7 ++-
1 file changed, 6 inser
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