From: Aric Cyr
This DC version brings along:
- Enable FPO optimization
- Support for 6.75 GBps link rate
- Fixes to underflow, black screen and more
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
From: Anthony Koo
- New parameter to define extra vblank stretch required when
doing FPO + Vactive
- Pass in pipe index for FPO
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 14 +++---
1 file changed,
From: Alvin Lee
[Description]
Assign the correct info now that FW headers are promoted
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/d
From: Peichen Huang
[Why]
Some dock and mst monitor don't like to receive ClearPayloadIdTable
when mst_en is set to 0. And it doesn't make sense to do so in source
side, either.
[How]
Not send ClearyPayloadIdTable if mst_en is 0
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by:
From: Alvin Lee
[Description]
Enable optimization for preferring FPO if it achieves
a lower voltage level
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321
From: Alvin Lee
[Description]
If transitioning from an FPO config -> FPO config, we want
to keep cursor P-State force disallowed. Any other transition
from FPO config -> non FPO config should unforce the cursor
P-State disallow
Reviewed-by: Wesley Chalmers
Acked-by: Qingqing Zhuo
Signed-off-by
From: Artem Grishin
[Why]
The 6.75 GBps link rate is part of the new eDP specification
version 1.5 is going to be supported in the future.
Since this standard is very new and there are no existing 6.75 GBps
panels on the market yet, we should put a condition in the driver
on enabling this featur
From: Alvin Lee
[Description]
* Pass in pipe index for FPO cmd to DMCUB
- This change will pass in the pipe index for each stream
that is using FPO
- This change is in preparation to enable FPO + VActive
* Use per pipe P-State force for FPO
- For FPO, instead of using max watermarks value fo
From: Artem Grishin
[Why]
The latest eDP spec version 1.5 defines a new generic link
rate of 6.75 Gbps/Lane, which needs to be supported in the driver.
[How]
Added new element to the dc_link_rate enum
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Artem Grishin
---
drivers
From: Ayush Gupta
[Why]
Observing underflow on dcn30+ system config at 4k144hz
[How]
We set the UCLK hardmax on AC/DC switch if softmax is enabled
and also on boot. While booting up the UCLK Hardmax is set
to softmax before the init sequence and the init sequence
resets the hardmax to UCLK max w
As part of the FAMS work, we need code infrastructure in DC.
dcn30_fpu.c changes went missing during previous upstream
activity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 53 ---
1 file
From: Taimur Hassan
[Why & How]
Needed to get certain EDID to light up during TMDS compliance.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/
From: Dmytro Laktyushkin
[Why & How]
w/a for dcn315 inconsistent smu clock.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/dri
From: Charlene Liu
[why]
HW delta follow up
Reviewed-by: Chris Park
Reviewed-by: Jun Lei
Reviewed-by: Jerry Zuo
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 10 +-
.../amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
From: Martin Leung
[Why & How]
when trying to fix a nullptr dereference on VMs,
accidentally doubly allocated memory for the non VM
case. removed the extra link_srv creation since
dc_construct_ctx is called in both VM and non VM cases
Also added a proper fail check for if kzalloc fails
Cc: sta..
From: Alvin Lee
[Descrtipion]
- Driver hardcoded FCLK P-State latency was incorrect
- Use the value provided by PMFW header instead
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2
From: Nicholas Kazlauskas
[Why]
DPP Root clock optimization when combined with 4to1 MPC combine results
in the screen turning black.
This is because the DPPCLK is stopped during the middle of an
optimize_bandwidth sequence during commit_minimal_transition without
going through plane power down/p
From: Alvin Lee
[Description]
- On high refresh rate DRR displays that support VBLANK naturally,
UCLK could be idling at DPM1 instead of DPM0 since it doesn't use
FPO
- To achieve DPM0, enable FPO on these configs even though it can
support P-State without FPO
- Default disable for now, hav
From: Nicholas Kazlauskas
[Why]
While scanning the top_pipe connections we can run into a case where
the bottom pipe is still connected to a top_pipe but with a NULL
plane_state.
[How]
Treat a NULL plane_state the same as the plane being invisible for
pipe cursor disable logic.
Cc: sta...@vger.
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Enable FPO optimization
- Support for 6.75 GBps link rate
- Fixes to underflow, black screen and more
Cc: Daniel Wheeler
---
Alvin Lee (6):
drm/amd/display: Enable FPO for configs that could reduce vlevel
d
On 3/23/2023 11:36 PM, Limonciello, Mario wrote:
On 3/23/2023 12:41, Limonciello, Mario wrote:
On 3/22/2023 00:48, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
dr
[AMD Official Use Only - General]
> -Original Message-
> From: Limonciello, Mario
> Sent: Friday, March 24, 2023 1:42 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Li, Ying ; Liu, Kun ; amd-
> g...@lists.freedesktop.org; Liang, Richard qi
> Sub
[AMD Official Use Only - General]
> -Original Message-
> From: Limonciello, Mario
> Sent: Friday, March 24, 2023 1:15 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Li, Ying ; Liu, Kun ; amd-
> g...@lists.freedesktop.org; Liang, Richard qi
> Sub
Hi Wenyou Yang, first of all thanks for the improvement!
I'd like to ask you (and all CCed) if it would be possible to explain a
bit the goal / functionality behind these patches.
By reading the commit descriptions and code, I can understand code-wise
what's going on and how this will message the
On Fri, Mar 24, 2023 at 05:34:18AM +0800, kernel test robot wrote:
> tree/branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> branch HEAD: 7c4a254d78f89546d0e74a40617ef24c6151c8d1 Add linux-next
> specific files for 20230323
>
> Err
Provide a debugfs interface to access the MQD. Useful for
debugging issues with the CP and MES hardware scheduler.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-
It varies by generation and we need to know the size
to expose this via debugfs.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/g
So UMDs can determine whether the kernel supports this.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
Use the new callback to fetch the data. Return an error if
not supported. UMDs should use this query to check whether
shadow buffers are supported and if so what size they
should be.
v2: return an error rather than a zerod structure.
v3: drop GDS, move into dev_info structure. Data will be
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 10 ++
1 file changed, 10 insertio
Only set the supported flag if we have new enough CP FW.
XXX: don't commit this until the CP FW versions are finalized!
Acked-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/
Used to get the size and alignment requirements for
the gfx shadow buffer for preemption.
v2: use FW version check to determine whether to
return a valid size here
return an error if not supported (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_
We need to reset the shadow state every time we submit an
IB and there needs to be a COND_EXEC packet after the
SET_Q_PREEMPTION_MODE packet for it to work properly, so
we should emit both of these packets regardless of whether
there is a job present or not.
Reviewed-by: Christian König
Signed-of
For GFX11, the UMD needs to allocate some shadow buffers
to be used for preemption. The UMD allocates the buffers
and passes the GPU virtual address to the kernel since the
kernel will program the packet that specified these
addresses as part of its IB submission frame.
v2: UMD passes shadow init
Add UAPI to query the GFX shadow buffer requirements
for preemption on GFX11. UMDs need to specify the shadow
areas for preemption.
v2: move into existing asic info query
drop GDS as its use is determined by the UMD (Marek)
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 8
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMDGPU_CHUNK_ID_CP_GFX_SHADOW in
amdgpu_cs_pa
Use this to determine if we support the new SET_Q_PREEMPTION_MODE
packet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on first use
Only set IB_VMID when a valid shad
This patch set allows for FW assisted shadowing on supported
platforms. A new enough CP FW is required. This feature is
required for mid command buffer preemption and proper SR-IOV
support. This also simplifies the UMDs by allowing persistent
hardware state when the command submission executes.
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 7c4a254d78f89546d0e74a40617ef24c6151c8d1 Add linux-next specific
files for 20230323
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com
https
Sorry, I think that was just a stray comment that I messed up while
editing my response. You can ignore it.
Regards,
Felix
Am 2023-03-23 um 15:12 schrieb Kim, Jonathan:
index c06ada0844ba..a2ac98d06e71 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Monday, March 20, 2023 8:31 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 19/32] drm/amdkfd: add runtime enable operation
>
>
> On 202
[AMD Official Use Only - General]
Hello Rodrigo and Harry,
I would like to propose some changes to keep this patch consistent with the
naming scheme and general organization of the drm_dp.h file.
#define DP_EDP_OLED_VESA_BRIGHTNESS_ON 0x80
It would be better to use the (1<<7) representation
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Thursday, February 16, 2023 6:44 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 03/32] drm/amdkfd: prepare per-process debug enable
> and disable
>
>
> On 2023-
On Tue, Mar 21, 2023 at 11:47 PM Christian König
wrote:
>
> Hi Mikhail,
>
> That looks like a reference counting issue to me.
>
> I'm going to take a look, but we have already fixed one of those recently.
>
> Probably best that you try this on drm-fixes, just to double check that
> this isn't the
On 3/23/2023 12:41, Limonciello, Mario wrote:
On 3/22/2023 00:48, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41
On 3/22/2023 00:48, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++
drivers/gpu/drm/amd/pm/swsmu/
On 3/22/2023 00:48, Wenyou Yang wrote:
Add the support to PPSMC_MSG_SetCClkSMTEnable(0x58) message to pmfw
for vangogh.
Signed-off-by: Wenyou Yang
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../gpu/drm/amd/pm/swsmu/smu
Hi Dave, Daniel,
Fixes for 6.3.
The following changes since commit e8d018dd0257f744ca50a729e3d042cf2ec9da65:
Linux 6.3-rc3 (2023-03-19 13:27:55 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.3-2023-03-23
for you to fetch
Am 2023-03-23 um 09:50 schrieb Kim, Jonathan:
[Public]
-Original Message-
From: Kuehling, Felix
Sent: Monday, March 20, 2023 5:50 PM
To: Kim, Jonathan ; amd-
g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 15/32] drm/amdkfd: prepare trap workaround for
[AMD Official Use Only - General]
Thanks a lot Luben!, much appreciate for your help!
-Original Message-
From: Tuikov, Luben
Sent: Thursday, March 23, 2023 7:24 PM
To: Koenig, Christian ; SHANMUGAM, SRINIVASAN
; Deucher, Alexander ;
Limonciello, Mario ; Zhang, Hawking
Cc: amd-gfx@li
On 2023-03-23 09:29, Christian König wrote:
> Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam:
>> CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with
>> non-zero value always evaluates to true
>> [-Werror,-Wtautological-bitw
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Monday, March 20, 2023 5:50 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 15/32] drm/amdkfd: prepare trap workaround for gfx11
>
>
> On 2023-01-25 14:53, Jonat
[Public]
Thanks a lot Mario!, much appreciate for your help in reviewing!
Best Regards,
Srini
-Original Message-
From: Limonciello, Mario
Sent: Thursday, March 23, 2023 6:09 PM
To: SHANMUGAM, SRINIVASAN ; Koenig, Christian
; Deucher, Alexander ; Li,
Candice ; Zhang, Hawking
Cc: amd-
[AMD Official Use Only - General]
Thanks a lot Hawking!, much appreciate for your help in reviewing!
Best Regards,
Srini
-Original Message-
From: Zhang, Hawking
Sent: Thursday, March 23, 2023 7:15 PM
To: Koenig, Christian ; SHANMUGAM, SRINIVASAN
; Deucher, Alexander ;
Limonciello, Ma
[AMD Official Use Only - General]
Thanks a lot Christian!, much appreciate for your help!
Best Regards,
Srini
-Original Message-
From: Koenig, Christian
Sent: Thursday, March 23, 2023 6:59 PM
To: SHANMUGAM, SRINIVASAN ; Deucher, Alexander
; Limonciello, Mario ;
Zhang, Hawking ; Tuiko
[AMD Official Use Only - General]
Good catch. This is a typo
The change is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Koenig, Christian
Sent: Thursday, March 23, 2023 21:29
To: SHANMUGAM, SRINIVASAN ; Deucher, Alexander
; Limonciello, Mario ;
Zhang, Hawkin
Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam:
CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with
non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare]
if (adev->ras_hw_enabled | AM
Series is:
Reviewed-by: Alex Deucher
On Thu, Mar 23, 2023 at 2:06 AM Luben Tuikov wrote:
>
> As soon as control->i2c_address is set, return; remove the "break;" from the
> switch--it is unnecessary. This mimics what happens when for some cases in the
> switch, we call helper functions with "retu
We are seeking nominations for candidates for election to the X.org
Foundation Board of Directors. However, as we presently do not have
enough nominations to start the election - the decision has been made to
extend the timeline by 2 weeks. Note this is a fairly regular part of
the elections proces
[Public]
> -Original Message-
> From: SHANMUGAM, SRINIVASAN
>
> Sent: Thursday, March 23, 2023 07:37
> To: Limonciello, Mario ; Koenig, Christian
> ; Deucher, Alexander
> ; Li, Candice ;
> Zhang, Hawking
> Cc: amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amd/amdgpu: Fix log
[Public]
Hi Mario,
Thanks for your comments, it was on " origin/amd-staging-drm-next"
Best Regards,
Srini
-Original Message-
From: Limonciello, Mario
Sent: Thursday, March 23, 2023 6:03 PM
To: SHANMUGAM, SRINIVASAN ; Koenig, Christian
; Deucher, Alexander ; Li,
Candice ; Zhang, Hawk
[Public]
> -Original Message-
> From: SHANMUGAM, SRINIVASAN
>
> Sent: Thursday, March 23, 2023 07:32
> To: Koenig, Christian ; Deucher, Alexander
> ; Limonciello, Mario
> ; Li, Candice ; Zhang,
> Hawking
> Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
>
> Subject: [PATCH] d
CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with
non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare]
if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF)
CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with
non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare]
if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF)
On 3/23/2023 3:04 PM, Yang, WenYou wrote:
[AMD Official Use Only - General]
-Original Message-
From: Lazar, Lijo
Sent: Thursday, March 23, 2023 4:29 PM
To: Yang, WenYou ; Deucher, Alexander
; Koenig, Christian
; Pan, Xinhui
Cc: Yuan, Perry ; Li, Ying ; amd-
g...@lists.freedesktop
[AMD Official Use Only - General]
> -Original Message-
> From: Yuan, Perry
> Sent: Thursday, March 23, 2023 10:21 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Liang, Richard qi ; Li, Ying
> ; Liu, Kun ; amd-
> g...@lists.freedesktop.org; Yang,
[AMD Official Use Only - General]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, March 23, 2023 4:29 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Liu, Kun ; Liang, Richard
[AMD Official Use Only - General]
Reviewed-by: Candice Li
Thanks,
Candice
-Original Message-
From: amd-gfx On Behalf Of Stanley.Yang
Sent: Thursday, March 23, 2023 4:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Stanley
Subject: [PATCH Review 1/1] drm/amdgpu: print ras drv fw de
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 6d2879ac585b..f76b1cb8baf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgp
Added AMD_IP_BLOCK_TYPE_MES to the list of engine
under amdgpu_device_ip_reinit_late_sriov, so that MES engine can be
correctly reset in SRIOV environment
Signed-off-by: Bill Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/
On 3/22/2023 2:46 PM, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++
drivers/gpu/drm/amd/pm/s
[AMD Official Use Only - General]
> -Original Message-
> From: Quan, Evan
> Sent: Thursday, March 23, 2023 3:17 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Yang, WenYou ; Liu,
> Kun ;
[AMD Official Use Only - General]
Thanks Evan.
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Wenyou Yang
> > Sent: Wednesday, March 22, 2023 5:16 PM
> > To: Deucher, Alexander ; Koenig,
> Christian
> > ; Pan, Xinhui
> > Cc: Yuan, Perry ; Li, Ying ;
> amd-
> > g...@lists.free
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Wenyou Yang
> Sent: Wednesday, March 22, 2023 5:16 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Yang, WenYou ; Liu,
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Wenyou Yang
> Sent: Wednesday, March 22, 2023 5:16 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Yang, WenYou ; Liu,
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