> -Original Message-
> From: Zhang, Hawking
> Sent: Monday, March 6, 2023 10:32 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Yang, Stanley ; Li, Candice ;
> Chai, Thomas
> Cc: Zhang, Hawking
> Subject: [PATCH 10/11] drm/amdgpu: Rework pcie_bif ras sw_init
>
> pcie_bif ras b
> -Original Message-
> From: Zhang, Hawking
> Sent: Monday, March 6, 2023 10:32 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Yang, Stanley ; Li, Candice ;
> Chai, Thomas
> Cc: Zhang, Hawking
> Subject: [PATCH 09/11] drm/amdgpu: Rework xgmi_wafl_pcs ras sw_init
>
> To align
[Why]
If disable the mmhub vm contexts(set MMVM_CONTEXTS_DISABLE to 0x),
driver loading failed on vf due to fence fallback timer expired on all rings.
FLR cannot reset MMVM_CONTEXTS_DISABLE.
So this vf can not be recovered anymore unless trigger a whole gpu reset.
[How]
Under SRIOV, init MMVM_
> -Original Message-
> From: Zhang, Hawking
> Sent: Monday, March 6, 2023 10:32 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Yang, Stanley ; Li, Candice ;
> Chai, Thomas
> Cc: Zhang, Hawking
> Subject: [PATCH 08/11] drm/amdgpu: Rework mca ras sw_init
>
> To align with other
Pinned objects that are not kfd objects reduce the total vram available
to kfd, so we subtract the total size of pinned objects from kdf vram
availability. However this double counts objects pinned by kfd itself
because they are counted both as used and pinned. So track the total
size of objects pi
Am 06.03.23 um 04:01 schrieb WANG Xuerui:
On 2023/3/6 10:49, Huacai Chen wrote:
Hi, Christian,
On Mon, Mar 6, 2023 at 12:40 AM Christian König
wrote:
Am 05.03.23 um 06:21 schrieb Huacai Chen:
LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, whic
I have one additional suggestion, the amdgpu_gfx_ras_sw_init is declared twice
in amdgpu_gfx.h file, it can be removed one in this patch.
Regards,
Stanley
> -Original Message-
> From: Zhang, Hawking
> Sent: Monday, March 6, 2023 10:32 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> -Original Message-
> From: Zhang, Hawking
> Sent: Monday, March 6, 2023 10:32 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Yang,
> Stanley ; Li, Candice ; Chai,
> Thomas
> Cc: Zhang, Hawking
> Subject: [PATCH 01/11] drm/amdgpu: Move jpeg ras block init to ras sw_init
>
> In
On 3/2/2023 9:05 PM, Lazar, Lijo wrote:
On 3/2/2023 8:56 PM, Deucher, Alexander wrote:
[AMD Official Use Only - General]
-Original Message-
From: Quan, Evan
Sent: Thursday, March 2, 2023 4:31 AM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org;
Deucher, Alexander
Subject: RE: [PA
[AMD Official Use Only - General]
Acked-by: Kenneth Feng
-Original Message-
From: amd-gfx On Behalf Of Perry Yuan
Sent: Friday, February 24, 2023 4:33 PM
To: Deucher, Alexander ; Quan, Evan
; Lazar, Lijo ; Li, Candice
; amd-gfx@lists.freedesktop.org
Cc: Huang, Shimmer ; Liu, Kun
Sub
[AMD Official Use Only - General]
Series is reviewed-by: Evan Quan
> -Original Message-
> From: Yuan, Perry
> Sent: Friday, February 24, 2023 4:33 PM
> To: Deucher, Alexander ; Quan, Evan
> ; Lazar, Lijo ; Li, Candice
> ; amd-gfx@lists.freedesktop.org
> Cc: Huang, Shimmer ; Liu, Kun
>
Hi, Christian,
On Mon, Mar 6, 2023 at 12:40 AM Christian König
wrote:
>
> Am 05.03.23 um 06:21 schrieb Huacai Chen:
> > LoongArch maintains cache coherency in hardware, but its WUC attribute
> > (Weak-ordered UnCached, which is similar to WC) is out of the scope of
> > cache coherency machanism.
amdgpu_ras_register_ras_block should always be invoked
by ras_sw_init, where driver needs to check ras caps
at ip level, instead of asic level.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
pcie_bif ras blocks needs to be initialized as early
as possible to handle fatal error detected in hw_init
phase. also align the pcie_bif ras sw_init with other
ras blocks
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 23 +++
drivers/gpu/drm/amd/
To align with other IP blocks.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 28 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 7 ++
4
To align with other IP blocks
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 21
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 72 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h | 9 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 15 +++---
dr
Initialize hdp ras block only when mmhub ip block
supports ras features. Driver queries ras capabilities
after early_init, ras block init needs to be moved to
sw_init.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +
Initialize mmhub ras block only when mmhub ip block
supports ras features. Driver queries ras capabilities
after early_init, ras block init needs to be moved to
sw_init.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
Initialize umc ras block only when umc ip block
supports ras. Driver queries ras capabilities after
early_init, ras block init needs to be moved to
sw_init.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 +
Initialize sdma ras block only when sdma ip block
supports ras features.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 9 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 9 ++---
3 files changed, 20 ins
Initialize gfx ras block only when gfx ip block
supports ras features.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++---
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/
Initialize vcn ras block only when vcn ip block
supports ras features. Driver queries ras capabilities
after early_init, ras block init needs to be moved to
sw_int.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29 -
drivers/gpu/drm/amd/amdgpu
Initialize jpeg ras block only when jpeg ip block
supports ras features. Driver queries ras capabilities
after early_init, ras block init needs to be moved to
sw_int.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 29
drivers/gpu/drm/amd/amdg
We are moving from soc ras to ip ras to address issues
as follows
- RAS sw block init is mixed in early_init and sw_init
- RAS cap check is mixed with both soc check and ip check.
RAS cap check is now only avaialble in amdgpu_ras_init,
based on the cap query from bios. RAS sw block init is
all mov
Am 05.03.23 um 06:21 schrieb Huacai Chen:
LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions. So use uncached ioremap()
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