Am 14.12.22 um 23:16 schrieb Alex Deucher:
gfxhub registers are part of gfx IP and should not need to be
changed. Doing so without disabling gfxoff can hang the gfx IP.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 --
1 file changed, 20
Add the support for WINDOW3D profile mode as for other profile modes.
Signed-off-by: Evan Quan
Change-Id: If05d1c7cbe5b6bc9f9c3c5036c01f6580d534164
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/am
To fit the latest PMFW and suppress the warning emerged on driver loading.
Signed-off-by: Evan Quan
Change-Id: Ia81ffdc8969a3b667454aa35c6d05d9de238ebcd
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h| 1
Add the missing declaration of struct drm_atomic_state to fix the
compile error below:
error: 'struct drm_atomic_state' declared inside parameter
list will not be visible outside of this definition or declaration [-Werror]
Signed-off-by: Ma Jun
---
include/drm/drm_plane_helper.h | 1 +
1 file c
On 2022-12-14 22:02, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:54 PM Robin Murphy wrote:
On 2022-12-12 02:08, Luben Tuikov wrote:
Fix screen corruption on older 32-bit systems using AGP chips.
On older systems with little memory, for instance 1.5 GiB, using an AGP chip,
the device's DMA
On 2022-12-14 16:06, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:56 PM Alex Hung wrote:
On 2022-12-14 15:35, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:25 PM Alex Hung wrote:
On 2022-12-14 14:54, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
On 2022
On Wed, Dec 14, 2022 at 5:56 PM Alex Hung wrote:
>
>
>
> On 2022-12-14 15:35, Alex Deucher wrote:
> > On Wed, Dec 14, 2022 at 5:25 PM Alex Hung wrote:
> >>
> >>
> >>
> >> On 2022-12-14 14:54, Alex Deucher wrote:
> >>> On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
>
>
>
> O
On 2022-12-14 15:35, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:25 PM Alex Hung wrote:
On 2022-12-14 14:54, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
On 2022-12-14 13:48, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote:
Fr
On 2022-12-14 10:42, Philip Yang wrote:
If kfd_process_device_init_vm returns failure after vm is converted to
compute vm and vm->pasid set to compute pasid, KFD will not take
pdd->drm_file reference. As a result, drm close file handler maybe
called to release the compute pasid before KFD process
On Wed, Dec 14, 2022 at 5:25 PM Alex Hung wrote:
>
>
>
> On 2022-12-14 14:54, Alex Deucher wrote:
> > On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
> >>
> >>
> >>
> >> On 2022-12-14 13:48, Alex Deucher wrote:
> >>> On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
> >>> wrote:
>
> Fr
On 2022-12-14 14:54, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
On 2022-12-14 13:48, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote:
From: Alex Hung
[Why]
When running IGT kms_bw test with DP monitor, some systems crash from
msle
This reverts commit e5d59cfa330523e47cba62a496864acc3948fc27.
This is no longer needed since we no longer suspend SDMA during
S0ix.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v
SDMA 5.x is part of the GFX block so it's controlled via
GFXOFF. Skip suspend as it should be handled the same
as GFX.
v2: drop SDMA 4.x. That requires special handling.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
1 file changed, 6 insertions(+)
dif
This reverts commit f543d28687480fad06b708bc6e0b0b6ec953b078.
This is no longer needed since we no longer touch SDMA 5.x for s0i3.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/
gfxhub registers are part of gfx IP and should not need to be
changed. Doing so without disabling gfxoff can hang the gfx IP.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/dri
gfxhub registers are part of gfx IP and should not need to be
changed. Doing so without disabling gfxoff can hang the gfx IP.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
gfxhub registers are part of gfx IP and should not need to be
changed. Doing so without disabling gfxoff can hang the gfx IP.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/dr
It's handled by GFXOFF for SDMA 5.x and SMU saves the state on
SDMA 4.x.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amd
This series improves S0ix stability by avoiding touching
registers that should be handled as part of gfxoff.
Alex Deucher (7):
drm/amdgpu/gmc9: don't touch gfxhub registers during S0ix
drm/amdgpu/gmc10: don't touch gfxhub registers during S0ix
drm/amdgpu/gmc11: don't touch gfxhub registers d
On Wed, Dec 14, 2022 at 4:54 PM Robin Murphy wrote:
>
> On 2022-12-12 02:08, Luben Tuikov wrote:
> > Fix screen corruption on older 32-bit systems using AGP chips.
> >
> > On older systems with little memory, for instance 1.5 GiB, using an AGP
> > chip,
> > the device's DMA mask is 0x, bu
On 2022-12-12 02:08, Luben Tuikov wrote:
Fix screen corruption on older 32-bit systems using AGP chips.
On older systems with little memory, for instance 1.5 GiB, using an AGP chip,
the device's DMA mask is 0x, but the memory mask is 0x7FF, and
subsequently dma_addressing_limited() r
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
>
>
>
> On 2022-12-14 13:48, Alex Deucher wrote:
> > On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
> > wrote:
> >>
> >> From: Alex Hung
> >>
> >> [Why]
> >> When running IGT kms_bw test with DP monitor, some systems crash from
> >> msleep no ma
On 2022-12-14 13:48, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote:
From: Alex Hung
[Why]
When running IGT kms_bw test with DP monitor, some systems crash from
msleep no matter how long or short the time is.
[How]
To replace msleep with mdelay.
Can you prov
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote:
>
> From: Alex Hung
>
> [Why]
> When running IGT kms_bw test with DP monitor, some systems crash from
> msleep no matter how long or short the time is.
>
> [How]
> To replace msleep with mdelay.
Can you provide a bit more info about the cra
From: Leo Chen
[Why & How]
For certain features, there will be more implementations needed in the if-block.
Braces are added as part of the preparation.
Acked-by: Aurabindo Pillai
Signed-off-by: Leo Chen
Reviewed-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file c
From: Aric Cyr
[why & how]
By moving bw_ctx field to the end of the dc_state the state can be
cleared more efficiently without resulting in large DML memcpy
operations, resulting in better mode enumeration performance on some
platforms.
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
Review
From: Leon Huang
[Why&How]
Recent ABM flow is highly coupled with backlight control on
LCD, refactor ABM control flow to be extensible to support different
panel types(e.g. LCD/OLED/miniLED)
Acked-by: Aurabindo Pillai
Signed-off-by: Leon Huang
Reviewed-by: Chun-Liang Chang
---
drivers/gpu/dr
From: Aric Cyr
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2896157b37da..0f7b7ccfcb40 100644
--- a
From: Leon Huang
[Why] Setting ABM pipe/backlight crashes the system when abm callback
func pointers are NULL For some usecase, driver would like to control
PWM level before ABM resource is ready. But recent flow refactor of ABM
didn't consider that use case.
[How] Rollback flow that sending inb
From: Wenjing Liu
[why]
During DP2.1 LL CTS if test equipment requests to change between
DP2.1 and DP1.4 link rates, we need to swap between HPO and DIO
encoders by remapping encoder resource.
[how]
Add a function dc resource to update encoder resources and toggle
dpms state for all enabled stre
From: Dmytro Laktyushkin
This function is meant to be used on multi-edp systems and only makes sense
if only links with connected panels are considered.
Acked-by: Aurabindo Pillai
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 15 +--
1 file chang
[Why&How]
ignore_msa_timing_param is used by SubVP logic to determine if SubVP
+ DRR is possible. Linux does not support freesync on multi display
config, which results in incorrect assumption of VRR support if we
set this parameter when VRR is supported, but not enabled.
Signed-off-by: Aurabindo
From: Wenjing Liu
[why]
Pixel rate div depends on the type of encoder
that we are enabling stream with. If we swap between
HPO and DIO encoder at the time we call enable stream
for the new encoder, we must reprogram pixel rate div
based on the new encoder type.
Acked-by: Aurabindo Pillai
Signed
From: Nicholas Kazlauskas
[Why]
On some monitors we see a brief flash of corruption during the
monitor disable sequence caused by FIFO being disabled in the middle
of an active DP stream.
[How]
Wait until DP vid stream is disabled before turning off the FIFO.
The FIFO reset on DP unblank should
From: Wenjing Liu
[why] dccg clock programming shouldn't be part of link hwss programming
sequence. The scope of link hwss is limited to encoder and phy
programming.
Acked-by: Aurabindo Pillai
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
---
.../display/dc/dce110/dce110_hw_sequencer.c |
From: "Lee, Alvin"
[Description]
- Proper phantom pipe disable sequence was missing in
commit_planes_for_stream
- If disabling phantom pipe, turn on phantom OTG first, and turn
off the phantom OTG after the plane is disabled
- Also update sequence for enabling / disabling phantom streams
(a
From: Alex Hung
[Why]
When running IGT kms_bw test with DP monitor, some systems crash from
msleep no matter how long or short the time is.
[How]
To replace msleep with mdelay.
Acked-by: Aurabindo Pillai
Signed-off-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/
From: Alan Liu
[Why]
- Need error message when failing to allocating secure_display_ctx.
- Need to check if secure display context in psp is initialized or not
before using it.
[How]
- Add error message when memory allocation fail.
- Add check before accessing psp secure display context.
Acked-
From: Swapnil Patel
[Why]
DCN301 resource function is missing function pointer to
handle cases with unknown plane state.
This causes assertion when global state is validated while
using swizzle parameter as “DC_UNKNOWN”
[How]
Add function pointer to handle and patch cases when plane
state is unk
From: Samson Tam
[Why]
SwathSizePerSurfaceY[] and SwathSizePerSurfaceC[] values are uninitialized
because we are using += instead of = operator.
[How]
Assign values in loop with = operator.
Acked-by: Aurabindo Pillai
Signed-off-by: Samson Tam
Reviewed-by: Aric Cyr
---
.../drm/amd/display/d
From: hersen wu
[Why]
multiple display hdcp are enabled within event_property_validate,
event_property_update by looping all displays on mst hub. when
one of display on mst hub in unplugged or disabled, hdcp are
disabled for all displays on mst hub within hdcp_reset_display
by looping all display
From: hersen wu
[Why]
connector hdcp properties are lost after display is
unplgged from mst hub. connector is destroyed with
dm_dp_mst_connector_destroy. when display is plugged
back, hdcp is not desired and it wouldnt be enabled.
[How]
save hdcp properties into hdcp_work within
amdgpu_dm_atomic
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fixes for various features like SubVP, ABM, HDCP, Secure display
* Fix a stability issue when running IGT test suite
* Improvements for eDP panels
-
Alan Liu (1):
drm/amd/display: Improvements in secure display
On Wed, Dec 14, 2022 at 3:56 AM Pekka Paalanen wrote:
>
> On Tue, 13 Dec 2022 11:32:01 -0500
> Harry Wentland wrote:
>
> > On 12/13/22 05:23, Pekka Paalanen wrote:
> > > On Mon, 12 Dec 2022 13:21:27 -0500
> > > Harry Wentland wrote:
> > >
> > >> Drivers might not support all colorspaces defined
On 12/14/22 03:55, Pekka Paalanen wrote:
> On Tue, 13 Dec 2022 11:32:01 -0500
> Harry Wentland wrote:
>
>> On 12/13/22 05:23, Pekka Paalanen wrote:
>>> On Mon, 12 Dec 2022 13:21:27 -0500
>>> Harry Wentland wrote:
>>>
Drivers might not support all colorspaces defined in
dp_colorsp
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 663397d1b469ff57f216d499b74a0b0183a508b8 Add linux-next specific
files for 20221214
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202211242120.mzzvguln-...@intel.com
https
On 2022-12-13 12:58, Felix Kuehling wrote:
On 2022-12-13 10:57, Christian König wrote:
Am 13.12.22 um 16:49 schrieb Philip Yang:
If amdgpu_amdkfd_gpuvm_acquire_process_vm returns failed after vm is
converted to KFD vm and vm->pasid set to KFD pasid, KFD will not
take pdd->drm_file reference,
On Wed, Dec 14, 2022 at 4:01 AM Pekka Paalanen wrote:
>
> On Tue, 13 Dec 2022 18:20:59 +0100
> Michel Dänzer wrote:
>
> > On 12/12/22 19:21, Harry Wentland wrote:
> > > This will let us pass kms_hdr.bpc_switch.
> > >
> > > I don't see any good reasons why we still need to
> > > limit bpc to 8 bpc
If kfd_process_device_init_vm returns failure after vm is converted to
compute vm and vm->pasid set to compute pasid, KFD will not take
pdd->drm_file reference. As a result, drm close file handler maybe
called to release the compute pasid before KFD process destroy worker to
release the same pasid
Should only destroy the ib_mem and let process cleanup worker to free
the outstanding BOs. Reset the pointer in pdd->qpd structure, to avoid
NULL pointer access in process destroy worker.
BUG: kernel NULL pointer dereference, address: 0010
Call Trace:
amdgpu_amdkfd_gpuvm_unmap_gtt_
On 10/26/22 07:48, Srinivasan Shanmugam wrote:
> Fix the following checkpatch checks in amdgpu_dm.c
>
> CHECK: Prefer kernel type 'u8' over 'uint8_t'
> CHECK: Prefer kernel type 'u32' over 'uint32_t'
> CHECK: Prefer kernel type 'u64' over 'uint64_t'
> CHECK: Prefer kernel type 's32' over 'int32
Add poison mode query support on df v4_3.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++
drivers/gpu/drm/amd/amdgpu/df_v4_3.c | 61 +++
drivers/gpu/dr
Add df v4_3 header files.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
---
.../amd/include/asic_reg/df/df_4_3_offset.h | 30
.../amd/include/asic_reg/df/df_4_3_sh_mask.h | 157 ++
2 files changed, 187 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include
Am 14.12.22 um 10:05 schrieb Luben Tuikov:
Remove the "domain" argument to amdgpu_bo_create_kernel_at() since this
function takes an "offset" argument which is the offset off of VRAM, and as
such allocation always takes place in VRAM. Thus, the "domain" argument is
unnecessary.
Cc: Alex Deucher
Am 14.12.22 um 10:41 schrieb Luben Tuikov:
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the
requested memory exists, else we get a kernel oops when dereferencing "man".
v2: Make the patch standalone, i.e. not dependent on local patches.
v3: Preserve old behaviour and
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the
requested memory exists, else we get a kernel oops when dereferencing "man".
v2: Make the patch standalone, i.e. not dependent on local patches.
v3: Preserve old behaviour and just check that the manager pointer is not
Remove the "domain" argument to amdgpu_bo_create_kernel_at() since this
function takes an "offset" argument which is the offset off of VRAM, and as
such allocation always takes place in VRAM. Thus, the "domain" argument is
unnecessary.
Cc: Alex Deucher
Cc: Christian König
Cc: AMD Graphics
Signe
On Tue, 13 Dec 2022 18:20:59 +0100
Michel Dänzer wrote:
> On 12/12/22 19:21, Harry Wentland wrote:
> > This will let us pass kms_hdr.bpc_switch.
> >
> > I don't see any good reasons why we still need to
> > limit bpc to 8 bpc and doing so is problematic when
> > we enable HDR.
> >
> > If I reme
On Tue, 13 Dec 2022 11:41:08 -0500
Harry Wentland wrote:
> On 12/13/22 05:39, Pekka Paalanen wrote:
> > On Mon, 12 Dec 2022 13:21:25 -0500
> > Harry Wentland wrote:
> >
> >> This allows us to use strongly typed arguments.
> >>
> >> Signed-off-by: Harry Wentland
> >> Cc: Pekka Paalanen
> >>
On Tue, 13 Dec 2022 11:32:01 -0500
Harry Wentland wrote:
> On 12/13/22 05:23, Pekka Paalanen wrote:
> > On Mon, 12 Dec 2022 13:21:27 -0500
> > Harry Wentland wrote:
> >
> >> Drivers might not support all colorspaces defined in
> >> dp_colorspaces and hdmi_colorspaces. This results in
> >> und
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