Configure related registers.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 66b3f42764df..0bc65b2f0ce8 100644
--- a/d
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue, and pops
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer Preemption for
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer.
Am 2022-11-28 um 22:47 schrieb Konstantin Meskhidze:
This patch fixes potential memory leakage and seg fault
in _gpuvm_import_dmabuf() function
Signed-off-by: Konstantin Meskhidze
Thank you for the patch. I'm adding a Fixes tag and pushing the patch to
amd-staging-drm-next.
Fixes: d4ec4bd
[AMD Official Use Only - General]
What I am thinking is that
Hi Chris,
For continuous memory allocation, of course the blocks are in ascending order.
For non-continuous memory allocation, the allocated memory might be continuous
while the blocks are not in ascending order.
Anyway, could we jus
[AMD Official Use Only - General]
Hi Arun,
Thanks for your reply. comments are inline.
发件人: Paneer Selvam, Arunpravin
发送时间: 2022年11月29日 1:09
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: linux-ker...@vger.kernel.org; dri-de...@lists.freedesktop.org;
On Tue, Nov 22, 2022 at 12:16 PM Christian König
wrote:
>
> Ah, thanks a lot for this. I've already pushed the patches into our
> internal branch, but getting this confirmation is still great!
>
> This was quite some fundamental bug in the handling and I hope to get
> this completely reworked at s
On Mon, Nov 28, 2022 at 09:50:50AM -0500, Alex Deucher wrote:
>>> [excessive quoting removed]
>> So, is there any progress on this issue? I do understand it's not a high
>>
>>
>> priority one, and to
Applied. Thanks!
Alex
On Fri, Nov 25, 2022 at 4:01 PM Randy Dunlap wrote:
>
> Fix documentation build errors for amdgpu: correct the filename.
>
> Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> Error: Canno
From: "Stanley.Yang"
[ Upstream commit 3cb93f390453cde4d6afda1587aaa00e75e09617 ]
[Why]
[ 754.862560] refcount_t: underflow; use-after-free.
[ 754.862898] Call Trace:
[ 754.862903]
[ 754.862913] amdgpu_job_free_cb+0xc2/0xe1 [amdgpu]
[ 754.863543] drm_sched_main.cold+
From: Dillon Varone
[ Upstream commit e667ee3b0c049bf0c69426879586a2572bb28d26 ]
[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager re
From: Taimur Hassan
[ Upstream commit 2a5dd86a69ea5435f1a837bdb7fafcda609a7c91 ]
[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.
[How]
Set valid divider values for virtual and FRL/DP2 cases.
Reviewed-by: Nicholas Kazlauskas
Acked-by:
From: Dillon Varone
[ Upstream commit dd2c028c1395d622df7ddd6837f8ab2dc94008ee ]
[WHY?]
MALL allocation size depends on the viewport height, not the addressable
vertical lines, which will not match when scaling.
[HOW?]
Base MALL allocation size calculations off viewport height.
Reviewed-by: Al
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 15f2f20ccbf2d04cb14e3e7635aa0447208c71e7 Add linux-next specific
files for 20221128
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202211041320.coq8eelj-...@intel.com
https
Am 27.11.22 um 06:39 schrieb xinhui pan:
Blocks are not guarnteed to be in ascending order.
Well certainly a NAK. Blocks are required to be in ascending order to be
contiguous.
Regards,
Christian.
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 21 -
Hi Xinhui,
On 11/28/2022 12:04 PM, xinhui pan wrote:
Currently drm-buddy does not have full knowledge of continuous memory.
Lets consider scenario below.
order 1:L R
order 0: LL LR RL RR
for order 1 allocation, it can offer L or R or LR+RL.
For now, we only impl
On Mon, Nov 28, 2022 at 2:18 AM Demi Marie Obenour
wrote:
>
> Dear Christian:
>
> What is the status of the AMDGPU work for Xen dom0? That was mentioned in
> https://lore.kernel.org/dri-devel/b2dec9b3-03a7-e7ac-306e-1da024af8...@amd.com/
> and there have been bug reports to Qubes OS about problem
On Mon, Nov 28, 2022 at 9:31 AM Mikhail Krylov wrote:
>
> On Mon, Apr 25, 2022 at 01:22:04PM -0400, Alex Deucher wrote:
> > + dri-devel
> >
> > On Mon, Apr 25, 2022 at 3:33 AM Krylov Michael wrote:
> > >
> > > Hello!
> > >
> > > After updating my Linux kernel from version 4.19 (Debian 10 version)
On Mon, Apr 25, 2022 at 01:22:04PM -0400, Alex Deucher wrote:
> + dri-devel
>
> On Mon, Apr 25, 2022 at 3:33 AM Krylov Michael wrote:
> >
> > Hello!
> >
> > After updating my Linux kernel from version 4.19 (Debian 10 version) to
> > 5.10 (packaged with Debian 11), I've noticed that the image
> >
The PID is racy, the user-space daemon could end up killing an
unrelated process… Is there any way we could use a pidfd instead?
On Fri, 25 Nov 2022 14:52:02 -0300
André Almeida wrote:
> From: Shashank Sharma
>
> Add a sysfs event to notify userspace about GPU resets providing:
> - PID that triggered the GPU reset, if any. Resets can happen from
> kernel threads as well, in that case no PID is provided
> - Information
On Fri, 25 Nov 2022 14:52:01 -0300
André Almeida wrote:
> This patchset adds a udev event for DRM device's resets.
Hi,
this seems a good idea to me.
> Userspace apps can trigger GPU resets by misuse of graphical APIs or driver
> bugs. Either way, the GPU reset might lead the system to a broken
On 20.11.22 18:25, Thorsten Leemhuis wrote:
> [Note: this mail is primarily send for documentation purposes and/or for
> regzbot, my Linux kernel regression tracking bot. That's why I removed
> most or all folks from the list of recipients, but left any that looked
> like a mailing lists. These
On Fri, 25 Nov 2022 12:07:48 + Lee Jones wrote:
> Since b339ec9c229aa ("kbuild: Only default to -Werror if COMPILE_TEST")
> WERROR
> now defaults to COMPILE_TEST meaning that it's enabled for allmodconfig
>
> builds. This leads to some interesting failures, each resolved in this s
Dear Christian:
What is the status of the AMDGPU work for Xen dom0? That was mentioned in
https://lore.kernel.org/dri-devel/b2dec9b3-03a7-e7ac-306e-1da024af8...@amd.com/
and there have been bug reports to Qubes OS about problems with AMDGPU
under Xen (such as https://github.com/QubesOS/qubes-issu
On Fri, 25 Nov 2022 12:07:48 + Lee Jones wrote:
> Since b339ec9c229aa ("kbuild: Only default to -Werror if COMPILE_TEST")
> WERROR
> now defaults to COMPILE_TEST meaning that it's enabled for allmodconfig
>
> builds. This leads to some interesting failures, each resolved in this s
Fix documentation build errors for amdgpu: correct the filename.
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
WARNING: kernel-doc '../scripts/ke
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