Hi Felix,
On 11/2/2022 3:38 AM, Felix Kuehling wrote:
>
> On 2022-11-01 04:52, Ma Jun wrote:
>> For some GPUs with more CUs, the original sibling_map[32]
>>
>> in struct crat_subtype_cache is not enough
>>
>> to save the cache information when create the VCRAT table,
>>
>> so skip filling the str
Configure related settings to enable it.
Signed-off-by: Tao Zhou
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
in
Prepare for enableing VCN RAS poison.
v2: move SHIFT and MASK definitions to related sh_mask.h file.
Signed-off-by: Tao Zhou
Signed-off-by: Lijo Lazar
---
.../amd/include/asic_reg/vcn/vcn_2_5_offset.h | 8 ++
.../include/asic_reg/vcn/vcn_2_5_sh_mask.h| 77 +++
2 files chan
On 11/1/2022 3:15 PM, Felix Kuehling wrote:
Checkpoint BOs last. That way we don't need to close dmabuf FDs if
something else fails later. This avoids problematic access to user mode
memory in the error handling code path.
criu_checkpoint_bos has its own error handling and cleanup that does no
On Tue, Nov 01, 2022 at 10:42:14AM -0400, Alex Deucher wrote:
> On Fri, Oct 28, 2022 at 11:32 PM Paulo Miguel Almeida
> wrote:
> >
> > One-element arrays are deprecated, and we are replacing them with
> > flexible array members instead. So, replace one-element array with
> > flexible-array member
On Tue, Nov 1, 2022 at 5:54 PM Kees Cook wrote:
>
> On Tue, Nov 01, 2022 at 10:42:14AM -0400, Alex Deucher wrote:
> > On Fri, Oct 28, 2022 at 11:32 PM Paulo Miguel Almeida
> > wrote:
> > >
> > > One-element arrays are deprecated, and we are replacing them with
> > > flexible array members instead
On Tue, Nov 1, 2022 at 5:14 PM Paulo Miguel Almeida
wrote:
>
> On Tue, Nov 01, 2022 at 10:42:14AM -0400, Alex Deucher wrote:
> > On Fri, Oct 28, 2022 at 11:32 PM Paulo Miguel Almeida
> > wrote:
> > >
> > > One-element arrays are deprecated, and we are replacing them with
> > > flexible array memb
On Tue, Nov 01, 2022 at 10:42:14AM -0400, Alex Deucher wrote:
> On Fri, Oct 28, 2022 at 11:32 PM Paulo Miguel Almeida
> wrote:
> >
> > One-element arrays are deprecated, and we are replacing them with
> > flexible array members instead. So, replace one-element array with
> > flexible-array member
On 2022-11-01 04:52, Ma Jun wrote:
For some GPUs with more CUs, the original sibling_map[32]
in struct crat_subtype_cache is not enough
to save the cache information when create the VCRAT table,
so skip filling the struct crat_subtype_cache info instead
fill struct kfd_cache_properties dire
On 10/20/2022 10:46, Rodrigo Siqueira wrote:
From: Max Tseng
Missing send cursor_rect width & Height into DMUB. PSR-SU would use
these information. But missing these assignment in last refactor commit
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Max Tseng
---
This wa
On 2022-11-01 14:49, Gavin Wan wrote:
The recent change brought a bug on SRIOV envrionment. It caused
kernel crashing while unloading amdgpu on guest VM with hive
configuration. The reason is that the hive->reset_domain is not
used (hive->reset_domain is not initialized) for SRIOV, but the
code d
On 2022-11-01 10:46, Graham Sider wrote:
Hang on MES timeout if halt_if_hws_hang is set to 1.
Signed-off-by: Graham Sider
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 4
drivers/gpu/drm/amd/amdgpu/mes_v11_
Checkpoint BOs last. That way we don't need to close dmabuf FDs if
something else fails later. This avoids problematic access to user mode
memory in the error handling code path.
criu_checkpoint_bos has its own error handling and cleanup that does not
depend on access to user memory.
Fixes: be072
The recent change brought a bug on SRIOV envrionment. It caused
kernel crashing while unloading amdgpu on guest VM with hive
configuration. The reason is that the hive->reset_domain is not
used (hive->reset_domain is not initialized) for SRIOV, but the
code did not check if hive->reset_domain befor
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: e9d267f752f8ff62f0111cea90e3ced4fc595b4f Add linux-next specific
files for 20221101
Error/Warning reports:
https://lore.kernel.org/linux-mm/202210090954.ptr6m6rj-...@intel.com
https
Hi Mikhail,
Am 30.10.22 um 23:05 schrieb Mikhail Gavrilov:
On Wed, Oct 26, 2022 at 12:29 PM Christian König
wrote:
Attached is the original test patch rebased on current amd-staging-drm-next.
Can you test if this is enough to make sure that the games start without
crashing by fetching the use
On Tue, Nov 01, 2022 at 10:36:08AM -0400, Rodrigo Siqueira Jordao wrote:
>
>
> On 2022-10-31 15:37, Ao Zhong wrote:
> > After moving all FPU code to the DML folder, we can enable DCN support
> > for the ARM64 platform. Remove the -mgeneral-regs-only CFLAG from the
> > code in the DML folder that
On Tue, Nov 1, 2022 at 11:42 AM Filip Moc wrote:
>
> Hello Alex,
>
> thank you for your response.
>
> Yes, I have HP ENVY x360 Convertible 13-ay1xxx, and backlight_min=2
> seems to work the best in my case.
>
> I added a dmi based quirk table. So far with support only for display 0
> to make it si
Hello Alex,
thank you for your response.
Yes, I have HP ENVY x360 Convertible 13-ay1xxx, and backlight_min=2
seems to work the best in my case.
I added a dmi based quirk table. So far with support only for display 0
to make it simple. Support for more displays in quirk table can be added
later i
Hello Harry,
thank you for your response.
> amdgpu.backlight_min=2:-1
almost :-)
Array elements in module parameters are separated by commas not colons.
So for cmdline it should look like this:
amdgpu.backlight_min=2,-1
Though you can just drop the ,-1 relying on kernel leaving the rest of arr
[AMD Official Use Only - General]
Hi Alex.
> -Original Message-
> From: Alex Deucher
> Sent: Tuesday, November 1, 2022 11:25 PM
> To: Yuan, Perry
> Cc: Deucher, Alexander ; Huang, Ray
> ; Huang, Shimmer ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/amdgpu: add Vangog
On Tue, Nov 1, 2022 at 11:19 AM Yuan, Perry wrote:
>
> [AMD Official Use Only - General]
>
> Hi Alex
>
> > -Original Message-
> > From: amd-gfx On Behalf Of Alex
> > Deucher
> > Sent: Tuesday, November 1, 2022 9:25 PM
> > To: Yuan, Perry
> > Cc: Deucher, Alexander ; Huang, Ray
> > ; Huan
[AMD Official Use Only - General]
Hi Alex
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, November 1, 2022 9:25 PM
> To: Yuan, Perry
> Cc: Deucher, Alexander ; Huang, Ray
> ; Huang, Shimmer ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] dr
Hang on MES timeout if halt_if_hws_hang is set to 1.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/am
[AMD Official Use Only - General]
> -Original Message-
> From: Sider, Graham
> Sent: Wednesday, October 26, 2022 5:05 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix ; Kasiviswanathan, Harish
> ; Cornwall, Jay
> ; Sider, Graham
> Subject: [PATCH] drm/amdkfd: update GFX11 CWS
On Fri, Oct 28, 2022 at 11:32 PM Paulo Miguel Almeida
wrote:
>
> One-element arrays are deprecated, and we are replacing them with
> flexible array members instead. So, replace one-element array with
> flexible-array member in struct _ATOM_FAKE_EDID_PATCH_RECORD and
> refactor the rest of the code
On 2022-10-31 15:37, Ao Zhong wrote:
After moving all FPU code to the DML folder, we can enable DCN support
for the ARM64 platform. Remove the -mgeneral-regs-only CFLAG from the
code in the DML folder that needs to use hardware FPU, and add a control
mechanism for ARM Neon.
Signed-off-by: Ao
Applied. Thanks!
Alex
On Mon, Oct 31, 2022 at 9:59 AM Harry Wentland wrote:
>
> On 2022-10-31 07:42, Jiri Slaby (SUSE) wrote:
> > rn_vbios_smu_set_dcn_low_power_state() produces a valid warning with
> > gcc-13:
> >
> > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c:237:6
On Tue, Nov 1, 2022 at 4:41 AM Yiqing Yao wrote:
>
> [why]
> Start from soc21, CP does not support MCBP, so disable it.
>
> [how]
> Used amgpu_mcbp flag alone instead of checking if is in SRIOV to
> enable/disable MCBP.
> Only set flag to enable on asic_type prior to soc21 in SRIOV.
>
> Signed-off
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Peng Ju Zhou
Sent: Monday, October 31, 2022 9:45 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: Remove unnecessary register program in SRIOV
Remove unnecessary register program in S
On Tue, Nov 1, 2022 at 9:23 AM Alex Deucher wrote:
>
> On Tue, Nov 1, 2022 at 1:16 AM Perry Yuan wrote:
> >
> > Add the missing apu flag for Vangogh when using IP discovery code path
> > to initialize IPs
> >
> > Signed-off-by: Perry Yuan
>
> Swap the order of the patches. With that, the series
On Tue, Nov 1, 2022 at 1:16 AM Perry Yuan wrote:
>
> Add the missing apu flag for Vangogh when using IP discovery code path
> to initialize IPs
>
> Signed-off-by: Perry Yuan
Swap the order of the patches. With that, the series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/
On Tue, Nov 1, 2022 at 2:52 AM Ville Syrjälä
wrote:
>
> On Mon, Oct 31, 2022 at 08:20:54PM -0400, Jason Baron wrote:
> >
> >
> > On 10/31/22 6:11 PM, jim.cro...@gmail.com wrote:
> > > On Mon, Oct 31, 2022 at 7:07 AM Ville Syrjälä
> > > wrote:
> > >> On Sun, Oct 30, 2022 at 08:42:52AM -0600, jim.c
From: Danijel Slivka
[ Upstream commit 65f8682b9aaae20c2cdee993e6fe52374ad513c9 ]
For asic with VF MMIO access protection avoid using CPU for VM table updates.
CPU pagetable updates have issues with HDP flush as VF MMIO access protection
blocks write to mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_F
From: Danijel Slivka
[ Upstream commit 65f8682b9aaae20c2cdee993e6fe52374ad513c9 ]
For asic with VF MMIO access protection avoid using CPU for VM table updates.
CPU pagetable updates have issues with HDP flush as VF MMIO access protection
blocks write to mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_F
From: YuBiao Wang
[ Upstream commit 2abe92c7adc9c0397ba51bf74909b85bc0fff84b ]
[Why]
If mes is not dequeued during fini, mes will be in an uncleaned state
during reload, then mes couldn't receive some commands which leads to
reload failure.
[How]
Perform MES dequeue via MMIO after all the unmap
From: Yifan Zha
[ Upstream commit 97a3d6090f5c2a165dc88bda05c1dcf9f08bf886 ]
[Why]
L1 blocks most of GC registers accessing by MMIO.
[How]
Use RLCG interface to program GC registers under SRIOV VF in full access time.
Signed-off-by: Yifan Zha
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
From: Nathan Chancellor
[ Upstream commit e688ba3e276422aa88eae7a54186a95320836081 ]
When booting a kernel compiled with CONFIG_CFI_CLANG on a machine with
an RX 6700 XT, there is a CFI failure in kfd_destroy_mqd_cp():
[ 12.894543] CFI failure at kfd_destroy_mqd_cp+0x2a/0x40 [amdgpu] (targe
From: Kenneth Feng
[ Upstream commit f700486cd1f2bf381671d1c2c7dc9000db10c50e ]
skip loading pptable from driver on secure board since it's loaded from psp.
Signed-off-by: Kenneth Feng
Reviewed-by: Guan Yu
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/pm/sw
From: Danijel Slivka
[ Upstream commit 65f8682b9aaae20c2cdee993e6fe52374ad513c9 ]
For asic with VF MMIO access protection avoid using CPU for VM table updates.
CPU pagetable updates have issues with HDP flush as VF MMIO access protection
blocks write to mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_F
On 2022-11-01 10:58, Zhu, Jiadong wrote:
>
>> Patch 3 assigns preempt_ib in gfx_v9_0_sw_ring_funcs_gfx, but not in
>> gfx_v9_0_ring_funcs_gfx. mux->real_ring in amdgpu_mcbp_trigger_preempt
>> presumably uses the latter, which would explain why amdgpu_ring_preempt_ib
>> ends up dereferencing a N
[AMD Official Use Only - General]
>Patch 3 assigns preempt_ib in gfx_v9_0_sw_ring_funcs_gfx, but not in
>gfx_v9_0_ring_funcs_gfx. mux->real_ring in amdgpu_mcbp_trigger_preempt
>presumably uses the latter, which would explain why amdgpu_ring_preempt_ib
>ends up dereferencing a NULL pointer.
It'
[ Please don't top-post ]
On 2022-11-01 02:04, Zhu, Jiadong wrote:
>
> It is a macro defined in amdgpu_ring.h, calling function pointer preempt_ib
> directly:
> #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
>
> The real ring's hook is assigned in gfx_v9_0.c:
> static const str
For some GPUs with more CUs, the original sibling_map[32]
in struct crat_subtype_cache is not enough
to save the cache information when create the VCRAT table,
so skip filling the struct crat_subtype_cache info instead
fill struct kfd_cache_properties directly to fix this problem.
v4:
- Fix th
On Mon, Oct 31, 2022 at 08:20:54PM -0400, Jason Baron wrote:
>
>
> On 10/31/22 6:11 PM, jim.cro...@gmail.com wrote:
> > On Mon, Oct 31, 2022 at 7:07 AM Ville Syrjälä
> > wrote:
> >> On Sun, Oct 30, 2022 at 08:42:52AM -0600, jim.cro...@gmail.com wrote:
> >>> On Thu, Oct 27, 2022 at 2:10 PM Ville
On 10/31/22 6:11 PM, jim.cro...@gmail.com wrote:
On Mon, Oct 31, 2022 at 7:07 AM Ville Syrjälä
wrote:
On Sun, Oct 30, 2022 at 08:42:52AM -0600, jim.cro...@gmail.com wrote:
On Thu, Oct 27, 2022 at 2:10 PM Ville Syrjälä
wrote:
On Thu, Oct 27, 2022 at 01:55:39PM -0600, jim.cro...@gmail.com w
[why]
Start from soc21, CP does not support MCBP, so disable it.
[how]
Used amgpu_mcbp flag alone instead of checking if is in SRIOV to
enable/disable MCBP.
Only set flag to enable on asic_type prior to soc21 in SRIOV.
Signed-off-by: Yiqing Yao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2
Use virt_init_setting instead of per ip version setting.
Signed-off-by: Yiqing Yao
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index e08044008186..
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