tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4d80748d16c82a9c2c4ea5feea96e476de3cd876 Add linux-next specific
files for 20221004
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209150141.wgbakqmx-...@intel.com
https
Implement the 3D LUT interface, convert and pass the data for amdgpu
driver.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++
.../gpu/drm/amd/displa
Enable the 3D LUT mode supported by amdgpu.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++
drivers/gpu/drm/drm_color_mgmt.c | 31 +
Add a 3D LUT mode supported by amdgpu driver.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/modules/color/color_gamma.h | 12
1 file changed, 12 insertions(+)
dif
Add plane lut_3d mode and lut_3d as blob properties.
lut_3d mode is an enum property with values as blob_ids.
Userspace can get supported modes and also set one of the modes.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off
A struct is defined for 3D LUT modes to be supported by hardware.
The elements includes lut_isze, lut_stride, bit_depth, color_format
and flags.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
include/ua
This is an proposal and a draft implementation to enable 3D LUT on
drm_plane. This proposal defines a new interface for userspace
applications to query hardware capabilities and to pass/enable 3D LUT
functions via this DRM/KMS APIs.
Overviews:
┌─┐┌─┐┌───┐┌──┐
On 2022-10-04 16:24, Lyude Paul wrote:
Yikes, it appears somehow I totally made a mistake here. We're currently
checking to see if drm_dp_add_payload_part2() returns a non-zero value to
indicate success. That's totally wrong though, as this function only
returns a zero value on success - not t
Yikes, it appears somehow I totally made a mistake here. We're currently
checking to see if drm_dp_add_payload_part2() returns a non-zero value to
indicate success. That's totally wrong though, as this function only
returns a zero value on success - not the other way around.
So, fix that.
Signed-
I'd prefer a separate patch and code review for the fini-case, because
that addresses a different (potential) problem.
Thanks,
Felix
On 2022-10-04 15:43, Philip Yang wrote:
On 2022-10-04 15:16, Felix Kuehling wrote:
On 2022-10-04 12:41, Philip Yang wrote:
amdkfd_total_mem_size is the siz
On 2022-10-04 15:16, Felix Kuehling wrote:
On 2022-10-04 12:41, Philip Yang wrote:
amdkfd_total_mem_size is the size of total GPUs vram plus system memory
to estimate page tables memory usage and leave enough VRAM room for page
tables allocation.
Calculate amdkfd_total_mem_size in amdgpu_amdk
On 2022-10-04 12:41, Philip Yang wrote:
amdkfd_total_mem_size is the size of total GPUs vram plus system memory
to estimate page tables memory usage and leave enough VRAM room for page
tables allocation.
Calculate amdkfd_total_mem_size in amdgpu_amdkfd_device_probe is
incorrect because adev->gmc
amdkfd_total_mem_size is the size of total GPUs vram plus system memory
to estimate page tables memory usage and leave enough VRAM room for page
tables allocation.
Calculate amdkfd_total_mem_size in amdgpu_amdkfd_device_probe is
incorrect because adev->gmc.real_vram_size is still 0 called from
amd
Am 04.10.22 um 16:08 schrieb Danijel Slivka:
CPU pagetable updates have issues with HDP flush as VF MMIO access
protection is not allowing write during sriov runtime to
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
The subject should have a drm/amdgpu prefix and in general Felix need to
On 2022-09-27 09:39, Yuan Can wrote:
After commit 5a8132b9f606("drm/amd/display: remove dead dc vbios code"), no one
use struct i2c_id_config_access, so remove it.
Signed-off-by: Yuan Can
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 7 ---
1 file changed, 7 deletions(-)
d
On 2022-09-30 02:38, Dong Chenchen wrote:
Kernel test robot throws below warning ->
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c:
In function 'dcn31_hpo_dp_stream_enc_update_dp_info_packets':
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hpo_dp_stre
CPU pagetable updates have issues with HDP flush as VF MMIO access
protection is not allowing write during sriov runtime to
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
Signed-off-by: Danijel Slivka
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +++-
1 file changed, 3 insertions(+), 1 de
Since 'hardwareActivityPerformanceLevels' is set to the size of the
'performance_levels' array in smu7_hwmgr_backend_init(), using the
'<=' assertion to check for the next index value is incorrect.
Replace it with '<'.
Detected using the static analysis tool - Svace.
Fixes: 599a7e9fe1b6 ("drm/amd/
Since 'hardwareActivityPerformanceLevels' is set to the size of the
'performance_levels' array in vega10_hwmgr_backend_init(), using the
'<=' assertion to check for the next index value is incorrect.
Replace it with '<'.
Detected using the static analysis tool - Svace.
Fixes: f83a9991648b ("drm/am
Hello,
It seems there is some dead or not-needed code. Either the if condition
isn't needed or condition is wrong. As this
greater-than-or-equal-to-zero comparison of an unsigned value is always
true. "version_minor >= 0". Please have a look at it.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_r
Am 03.10.22 um 19:20 schrieb Philip Yang:
Under VRAM usage pression, map to GPU may fail to create pt bo and
vmbo->shadow_list is not initialized, then ttm_bo_release calling
amdgpu_bo_vm_destroy to access vmbo->shadow_list generates below
dmesg and NULL pointer access backtrace:
Set vmbo destro
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