Alistair Popple writes:
> When the CPU tries to access a device private page the migrate_to_ram()
> callback associated with the pgmap for the page is called. However no
> reference is taken on the faulting page. Therefore a concurrent
> migration of the device private page can free the page and p
Michael Ellerman writes:
> Alistair Popple writes:
>> When the CPU tries to access a device private page the migrate_to_ram()
>> callback associated with the pgmap for the page is called. However no
>> reference is taken on the faulting page. Therefore a concurrent
>> migration of the device p
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, September 29, 2022 3:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/gfx10: ignore rlc ucode validation
There are apparently u
Looks OK to me.
Reviewed by : shaoyun.liu
From: Chander, Vignesh
Sent: September 28, 2022 3:03 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun ; Chander, Vignesh
Subject: [PATCH] drm/amdgpu: Skip put_reset_domain if it doesnt exist
For xgmi sriov, the
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
>
>
>
> On 9/27/2022 10:40 PM, Alex Deucher wrote:
> > On Tue, Sep 27, 2022 at 11:38 AM Sharma, Shashank
> > wrote:
> >>
> >>
> >>
> >> On 9/27/2022 5:23 PM, Felix Kuehling wrote:
> >>> Am 2022-09-27 um 10:58 schrieb Sharma, Shashank:
>
Re comments about infinite retry: gotcha, makes sense to me.
On Tue, 2022-09-27 at 09:45 +1000, Alistair Popple wrote:
> John Hubbard writes:
>
> > On 9/26/22 14:35, Lyude Paul wrote:
> > > > + for (i = 0; i < npages; i++) {
> > > > + if (src_pfns[i] & MIGRATE_PFN_MIGRATE) {
Reviewed-by: Lyude Paul
On Wed, 2022-09-28 at 22:01 +1000, Alistair Popple wrote:
> When the module is unloaded or a GPU is unbound from the module it is
> possible for device private pages to still be mapped in currently
> running processes. This can lead to a hangs and RCU stall warnings when
>
On Tue, 2022-09-27 at 11:39 +1000, Alistair Popple wrote:
> Felix Kuehling writes:
>
> > On 2022-09-26 17:35, Lyude Paul wrote:
> > > On Mon, 2022-09-26 at 16:03 +1000, Alistair Popple wrote:
> > > > When the module is unloaded or a GPU is unbound from the module it is
> > > > possible for device
From: Rodrigo Siqueira
This commit adds some minor code style changes just to reduce the merge
conflicts we have when we upstream some of the VBA code.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 9 ++---
1 f
From: Aric Cyr
This reverts commit bbd46fc8daae7c2a1c79b63854621d8446e9794a.
4K144 resolution isn't available on DCN31.
Reviewed-by: Sherry Wang
Acked-by: Hamza Mahfooz
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+),
From: Rodrigo Siqueira
Add HDMI ACP bit field definition for DCN32.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_
From: Eric Bernstein
[Why]
In DIO stream encoder, definition of DP_DSC_MODE is changed (only
enable/disable) In OPTC, OTG_SET_V_TOTAL_MIN_MASK_EN is removed (same as
DCN3.1)
[How]
In DIO stream encoder, update enc32_dp_set_dsc_config(). In OPTC, use
DCN3.1 version for function interfaces .set_vr
From: George Shen
[Why]
Certain features require the additional DP SDP configuration registers
DP_SEC_CNTL1 and DP_SEC_CNTL5 in order to function correctly.
The DCN32 DIO stream encoder reglist is currently missing these two
registers.
[How]
Add the missing registers to the DCN32 DIO stream enc
From: Rodrigo Siqueira
Under DCN32/321 we identified some code paths that DC never executes.
This commit removes those unused codes to avoid distractions when
debugging issues.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/dcn32/dcn32_dio_link_encoder.c | 7
From: Rodrigo Siqueira
Update DSC checks in the DCN32 VBA.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml
From: Aric Cyr
[how]
Large deltas for periodic interrupts could result in the interrupt not
being programmed properly and thus not firing.
[why]
Add proper wrap-around support for calculating VUPDATE and VLINE
positions.
Reviewed-by: Jun Lei
Acked-by: Hamza Mahfooz
Signed-off-by: Aric Cyr
--
From: Rodrigo Siqueira
[Why]
During transition from ODM combine to ODM bypass, if DSC is enabled need
to disconnect the DSC mux for pipes no longer in use.
[How]
During ODM update, detect pipes with DSC that are no longer being used
for new state and call new DSC interface to disconnect.
Add ne
From: "Leo (Hanghong) Ma"
[Why && How]
Remove the unnecessary AUX trace and use one trace for AUX failure.
Reviewed-by: Martin Leung
Acked-by: Hamza Mahfooz
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 13 +++--
1 file changed, 3 insertions(+),
From: Rodrigo Siqueira
At some point, we decided to blank HUBP during pixel data blank, and to
handle that, we added some OPTC lock checks. Later, we realized that
this change caused multiple regression, and we removed it. Nevertheless,
we still have some leftovers that might affect some ASIC beh
From: "Leung, Martin"
why and how:
needed to fix bad assumption for enable mcm_luts
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dis
From: Charlene Liu
[why]
limit the vm prefetch check for now, until the feature is fully
verified.
Reviewed-by: Hansen Dsouza
Acked-by: Hamza Mahfooz
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(
From: Rodrigo Siqueira
If the current configuration supports 2 to 1 ODM policy, let's also
enable the windowed MPO feature.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4
1 file changed, 4 insertions(+)
diff --gi
From: Lewis Huang
[Why]
Disable OTG when PSRSU with z10 even if z10 is disable
[How]
Reverse condition to keep OTG on when Z10 is disable
Reviewed-by: Robin Chen
Acked-by: Hamza Mahfooz
Signed-off-by: Lewis Huang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2
From: Zhikai Zhai
[WHY]
Now dynamic ODM will now be disabled when MPO is required safe
transitions to avoid underflow, but we are triggering the way of
minimal transition too often. Commit state of dc with no check
will do pipeline setup which may re-initialize the component with no
need such as
From: Leo Chen
[Why & How]
Adding log for LTTPR to facilitate debugging.
Reviewed-by: Charlene Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Leo Chen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 29 +++
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/driver
From: Wenjing Liu
There is a missing register mask in dcn32 causing the hardware
programming is not executed when programming SQ_num test pattern for
DP2.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h | 1 +
1 fil
From: Ian Chen
We split out ILR config from "global" to "per-panel" config settings.
Reviewed-by: Anthony Koo
Acked-by: Hamza Mahfooz
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 -
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 4 ++--
dri
From: Wenjing Liu
[why]
Analyzer shows incorrect V freq in MSA for some large timing.
[how]
Cast an 32 bit integer to uint64_t before multiplication to avoid
integer overflow for a very large timing.
Reviewed-by: Ariel Bernstein
Acked-by: Hamza Mahfooz
Signed-off-by: Wenjing Liu
---
.../drm
From: Dillon Varone
[WHY&HOW?]
When merging ODM pipes that are using MPO, we must copy the stream_res
from the new top pipe to the bottom pipe so that the overlayed plane is
not pointing to the wrong stream assets.
Reviewed-by: Martin Leung
Reviewed-by: Jun Lei
Acked-by: Hamza Mahfooz
Signed-
From: Aric Cyr
This version brings along following:
- ILR improvements
- PSR fixes
- DCN315 fixes
- DCN32 fixes
- ODM fixes
- DSC fixes
- SubVP fixes
Acked-by: Hamza Mahfooz
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Rodrigo Siqueira
For some reason, we missed the PState check for DCN32 which may cause
issues for clock transition. This commit add that required hook.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 1 +
1 file cha
From: Rodrigo Siqueira
DCN provides a hook to check if we can have a new pipe allocation based
on some DC constraints. If the current configuration supports the new
pipe request, DC updates its context; otherwise, it will keep the same
configuration. This behavior is similar across multiple ASICs
From: Rodrigo Siqueira
SubVP has some issues related to how we allocate and enable it. This
commit fixes this behavior by adding the proper check and configuration
to the SubVP code path.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.
From: Wenjing Liu
[why]
According to specs, it expects us to write all 4 bytes even if
current lane count is less than 4.
Reviewed-by: George Shen
Acked-by: Hamza Mahfooz
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 37 +--
1 file changed, 18
From: Martin Leung
why:
when dynamic odm was turned on, there is also logic to halve the pixelclk
this still turned on when we avoided odm in the case of odd h_total timings
how:
block the pixel clk mechanism also in the case of odd h_total timings
Reviewed-by: Jun Lei
Acked-by: Hamza Mahfooz
From: Alvin Lee
[Description]
- For SubVP pipe split case we need to use a minimial transition
when opening MPO video since we are transitioning from 4 pipes
to 3 pipes where an OPP for a previous MPCC will change
- Also save and restore mall config when doing fast_validate in case
there wa
From: Dillon Varone
[WHY?]
Clocks are updating based on the incoming context's support, however the new
compbuf size is not programmed prior to udpating clocks, which can result in
P-State hangs.
[HOW?]
Increase compbuf size prior to updating clocks.
Reviewed-by: Alvin Lee
Reviewed-by: Martin
From: Dmytro Laktyushkin
DML does not take the fact that dcn315 does not have enough detile
buffer to max all pipes. This change adds a workaround to apply
the same logic DC does when calculating detile buffer size in DML.
Reviewed-by: Charlene Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Dmytro
From: Alvin Lee
[Description]
When enabling phantom pipe on a pipe that was previously
using immediate flip, we have to disable GSL or this will
prevent the update from taking place right away on the phantom
pipe when we enable it in FW
Reviewed-by: Jun Lei
Acked-by: Hamza Mahfooz
Signed-off-b
From: Alvin Lee
[Description]
- SubVP rotation support is not explicitly implemented,
so block SubVP in rotation cases to avoid unexpected
behaviors
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Hamza Mahfooz
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_r
From: Iswara Nagulendran
[HOW&WHY]
Fixed check to only avoid PSR entry when panel
is disconnected. PSR exit can be permitted to restore
the HW to it's non-PSR state.
Reviewed-by: Jayendran Ramani
Acked-by: Hamza Mahfooz
Signed-off-by: Iswara Nagulendran
---
drivers/gpu/drm/amd/display/dc/cor
From: Dmytro Laktyushkin
DCN315 has to always allow pstate change or SMU will hang. This
workaround achieves this by applying a low pstate change latency
to be used when pstate is calculated to be unsupported. This lower
latency only accounts for memory retraining; a previous change
handles locki
From: Dillon Varone
[WHY?]
In some cases, DCFCLK hardmin requests are not acknowledged by SMU as
the requested clock does not have a compatible ratio with current FCLK,
and it cannot be changed as FCLK P-state is not allowed.
[HOW?]
Allow FCLK p-state change prior to changing DCFCLK hardmin.
Re
From: Dillon Varone
[Why?]
Currently SubVP programming is only done in commit_planes_for_stream, as
it was expected only this call would add/remove planes from a
display.
[How?]
Add SubVP programming to dc_commit_state_no_check.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Di
This DC patch-set brings improvements in multiple areas. In summary, we
highlight:
* ILR improvements;
* PSR fixes;
* DCN315 fixes;
* DCN32 fixes;
* ODM fixes;
* DSC fixes;
* SubVP fixes.
Cc: Daniel Wheeler
Alvin Lee (3):
drm/amd/display: Block SubVP if rotation being used
drm/amd/display:
On Wed, Sep 28, 2022 at 3:24 PM Dmitry Osipenko
wrote:
>
> On 9/28/22 20:47, Dmitry Osipenko wrote:
> > On 9/28/22 20:44, Deucher, Alexander wrote:
> >> [AMD Official Use Only - General]
> >>
> >> This should be fixed in a backwards compatible way with this patch:
> >> https://patchwork.freedeskto
There are apparently ucode versions in the wild with incorrect
sizes specified in the header. We never checked this before,
so don't start now.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2170
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++-
1 file ch
Prepare OMAP DRM driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletio
Prepare Armada driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/armada/armada_gem.c | 8
1 file changed, 4 insertions(+), 4 deletions(-
Add documentation for the dynamic locking convention. The documentation
tells dma-buf API users when they should take the reservation lock and
when not.
Acked-by: Sumit Semwal
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
---
Documentation/driver-api/dma-buf.rst | 6 +++
drivers
Prepare Tegra DRM driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gem.c | 17 +
1 file changed, 9 insertions(+), 8 deleti
All drivers that use dma-bufs have been moved to the updated locking
specification and now dma-buf reservation is guaranteed to be locked
by importers during the mapping operations. There is no need to take
the internal dma-buf lock anymore. Remove locking from the videobuf2
memory allocators.
Ack
Prepare fastrpc to the common dynamic dma-buf locking convention by
starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Acked-by: Srinivas Kandagatla
Signed-off-by: Dmitry Osipenko
---
drivers/misc/fastrpc.c | 6 +++---
1 file changed, 3 insertions(+), 3 d
Move dma_buf_mmap() function to the dynamic locking specification by
taking the reservation lock. Neither of the today's drivers take the
reservation lock within the mmap() callback, hence it's safe to enforce
the locking.
Acked-by: Sumit Semwal
Acked-by: Christian König
Signed-off-by: Dmitry Os
On 9/28/22 20:47, Dmitry Osipenko wrote:
> On 9/28/22 20:44, Deucher, Alexander wrote:
>> [AMD Official Use Only - General]
>>
>> This should be fixed in a backwards compatible way with this patch:
>> https://patchwork.freedesktop.org/patch/504869/
>
> Good to know that it's already addressed, tha
Hello,
This series moves all drivers to a dynamic dma-buf locking specification.
>From now on all dma-buf importers are made responsible for holding
dma-buf's reservation lock around all operations performed over dma-bufs
in accordance to the locking specification. This allows us to utilize
reserv
Move dma_buf_vmap/vunmap() functions to the dynamic locking
specification by asserting that the reservation lock is held.
Acked-by: Sumit Semwal
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 4
1 file changed, 4 insertions(+)
diff --git a/driver
The internal dma-buf lock isn't needed anymore because the updated
locking specification claims that dma-buf reservation must be locked
by importers, and thus, the internal data is already protected by the
reservation lock. Remove the obsoleted internal lock.
Acked-by: Sumit Semwal
Acked-by: Chri
Prepare gntdev driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Juergen Gross
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/xen/gntdev-dmabuf.c | 8
1 file changed, 4 insertions(
Prepare InfiniBand drivers to the common dynamic dma-buf locking
convention by starting to use the unlocked versions of dma-buf API
functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/infiniband/core/umem_dmabuf.c | 7 ---
1 file changed, 4 insertions(+), 3 delet
Prepare V4L2 memory allocators to the common dynamic dma-buf locking
convention by starting to use the unlocked versions of dma-buf API
functions.
Acked-by: Tomasz Figa
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/media/common/videobuf2/videobuf2-dma-contig.c | 11 +
Move dma-buf attachment API functions to the dynamic locking specification
by taking the reservation lock around the mapping operations. The strict
locking convention prevents deadlock situations for dma-buf importers and
exporters.
Acked-by: Sumit Semwal
Reviewed-by: Christian König
Signed-off-
Add unlocked variant of dma_buf_map/unmap_attachment() that will
be used by drivers that don't take the reservation lock explicitly.
Acked-by: Sumit Semwal
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 53 +++
inclu
Move dma-buf attachment mapping functions to the dynamic locking
specification by asserting that the reservation lock is held.
Acked-by: Sumit Semwal
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 10 ++
1 file changed, 2 insertions(+), 8 de
Prepare Etnaviv driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Prepare Tegra video decoder driver to the common dynamic dma-buf
locking convention by starting to use the unlocked versions of dma-buf
API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/media/platform/nvidia/tegra-vde/dmabuf-cache.c | 6 +++---
1 file changed,
Add unlocked variant of dma_buf_vmap/vunmap() that will be utilized
by drivers that don't take the reservation lock explicitly.
Acked-by: Sumit Semwal
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 41 +++
include/li
Prepare i915 driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions
and handling cases where importer now holds the reservation lock.
Acked-by: Christian König
Reviewed-by: Michael J. Ruhl
Signed-off-by: Dmitry Osipenko
---
dri
Prepare DRM prime core to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/drm_prime.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
dif
The new common dma-buf locking convention will require buffer importers
to hold the reservation lock around mapping operations. Make DRM GEM core
to take the lock around the vmapping operations and update DRM drivers to
use the locked functions for the case where DRM core now holds the lock.
This p
Am 2022-09-28 um 11:21 schrieb Graham Sider:
Simplify the logic in amdgpu_gmc_noretry_set by getting rid of the
switch. Also set noretry=1 as default for GFX 10.3.0 and greater since
retry faults are not supported.
Signed-off-by: Graham Sider
Reviewed-by: Felix Kuehling
---
drivers/gpu/
Inlined:
On 2022-09-28 14:49, Andrey Grodzovsky wrote:
> When many entities are competing for the same run queue
> on the same scheduler, we observe an unusually long wait
> times and some jobs get starved. This has been observed on GPUVis.
>
> The issue is due to the Round Robin policy used by s
For xgmi sriov, the reset is handled by host driver and hive->reset_domain
is not initialized so need to check if it exists before doing a put.
Signed-off-by: Vignesh Chander
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/driver
On Wed, Sep 28, 2022 at 11:22 AM Graham Sider wrote:
>
> Simplify the logic in amdgpu_gmc_noretry_set by getting rid of the
> switch. Also set noretry=1 as default for GFX 10.3.0 and greater since
> retry faults are not supported.
>
> Signed-off-by: Graham Sider
Acked-by: Alex Deucher
> ---
>
Am 2022-09-28 um 12:11 schrieb Philip Yang:
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscribe. When switching xnack mode from off to on,
subsequent free ranges allocated with xnac
When many entities are competing for the same run queue
on the same scheduler, we observe an unusually long wait
times and some jobs get starved. This has been observed on GPUVis.
The issue is due to the Round Robin policy used by schedulers
to pick up the next entity's job queue for execution. Un
Am 28.09.22 um 20:22 schrieb Vignesh Chander:
For xgmi sriov, the reset is handled by host driver and hive->reset_domain
is not initialized so need to check if it exists before doing a put.
Once more: General practice is to make the *_put_*() functions NULL
tolerant.
So rather make this than
For xgmi sriov, the reset is handled by host driver and hive->reset_domain
is not initialized so need to check if it exists before doing a put.
Signed-off-by: Vignesh Chander
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers
[AMD Official Use Only - General]
Hi Christian,
It is because the host driver handles the reset for xgmi sriov case. I will
update the commit body as
For xgmi sriov, the reset is handled by host driver and hive->reset_domain
is not initialized so need to check if it exists before doing a put.
On 9/28/22 20:44, Deucher, Alexander wrote:
> [AMD Official Use Only - General]
>
> This should be fixed in a backwards compatible way with this patch:
> https://patchwork.freedesktop.org/patch/504869/
Good to know that it's already addressed, thank you very much for the
quick reply.
--
Best re
On 9/24/22 10:14, Zhang, Hawking wrote:
> [Public]
>
> Hi Alex,
>
> Sienna cichlid rlc firmware binary needs to be updated to match with the
> kernel change.
>
> I shall add this comment to commit description.
>
> Regards,
> Hawking
>
> From: Deucher, Alexander
> Sent: Saturday, September 24
Am 28.09.22 um 19:43 schrieb Vignesh Chander:
For sriov, the reset domain is no longer created so need to check if it
exists before doing a put.
Why is the reset domain no longer created for SRIOV?
Regards,
Christian.
Signed-off-by: Vignesh Chander
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xg
[AMD Official Use Only - General]
Please add description like under sriov xgmi configuration , the hive reset is
handled by host driver , hive->reset_domain is not been in initialized so
need to skip it .
Regards
Shaoyun.liu
-Original Message-
From: Chander, Vignesh
Sent: Wednesd
Am 28.09.22 um 19:37 schrieb Vignesh Chander:
Change-Id: Ifd6121fb94db3fadaa1dee61d35699abe1259409
Signed-off-by: Vignesh Chander
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/d
[AMD Official Use Only - General]
This should be fixed in a backwards compatible way with this patch:
https://patchwork.freedesktop.org/patch/504869/
Alex
From: Dmitry Osipenko
Sent: Wednesday, September 28, 2022 1:40 PM
To: Zhang, Hawking ; Deucher, Alexander
;
For sriov, the reset domain is no longer created so need to check if it
exists before doing a put.
Signed-off-by: Vignesh Chander
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/
On 2022-09-28 13:37, Vignesh Chander wrote:
Change-Id: Ifd6121fb94db3fadaa1dee61d35699abe1259409
Signed-off-by: Vignesh Chander
Please remove the Change-Id and provide commit message body.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Change-Id: Ifd6121fb94db3fadaa1dee61d35699abe1259409
Signed-off-by: Vignesh Chander
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 47159e9
On 2022-09-28 10:53, Hamza Mahfooz wrote:
On 2022-09-28 10:49, sunpeng...@amd.com wrote:
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status' is used
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we observe that with PSR SU, it causes
visual artifacts, higher power usage, and potential system hang.
Thi
On 2022-09-28 09:52, Harry Wentland wrote:
On 2022-09-27 19:13, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we observe
On Wed, 28 Sep 2022 22:01:22 +1000 Alistair Popple wrote:
> @@ -1401,22 +1494,7 @@ static int dmirror_device_init(struct dmirror_device
> *mdevice, int id)
>
> static void dmirror_device_remove(struct dmirror_device *mdevice)
> {
> - unsigned int i;
> -
> - if (mdevice->devmem_chunks
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscribe. When switching xnack mode from off to on,
subsequent free ranges allocated with xnack off will not unreserve
memory. When switching
Am 2022-09-28 um 11:55 schrieb Philip Yang:
On 2022-09-27 14:58, Felix Kuehling wrote:
Am 2022-09-27 um 11:43 schrieb Philip Yang:
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscri
On 2022-09-27 14:58, Felix Kuehling wrote:
Am 2022-09-27 um 11:43 schrieb Philip Yang:
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscribe. When switching xnack mode from off to on
Simplify the logic in amdgpu_gmc_noretry_set by getting rid of the
switch. Also set noretry=1 as default for GFX 10.3.0 and greater since
retry faults are not supported.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 48 +
1 file changed, 9 inse
On 2022-09-28 16:46, Christian König wrote:
> Am 28.09.22 um 15:52 schrieb Michel Dänzer:
>> On 2022-09-28 03:01, Zhu, Jiadong wrote:>
>>> Please make sure umd is calling the libdrm function to create context with
>>> different priories,
>>> amdgpu_cs_ctx_create2(device_handle, AMDGPU_CTX_PRIORITY
On 2022-09-28 10:49, sunpeng...@amd.com wrote:
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status' is used uninitialized whenever 'if' condition
is fals
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status' is used uninitialized whenever 'if' condition
is false [-Werror,-Wsometimes-uninitialized]
if
Am 28.09.22 um 15:52 schrieb Michel Dänzer:
On 2022-09-28 03:01, Zhu, Jiadong wrote:>
Please make sure umd is calling the libdrm function to create context with
different priories,
amdgpu_cs_ctx_create2(device_handle, AMDGPU_CTX_PRIORITY_HIGH, &context_handle).
Yes, I double-checked that, and
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