[AMD Official Use Only - General]
Thanks Kevin!
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Wang, Yang(Kevin)
Date: Friday, September 9, 2022 at 11:50
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking , Wang, Yang(Kevin)
Subject: [PATCH v3] drm/amdgpu: change the alignment size of
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
v2:
add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu/drm/amd/amdgpu
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
v2:
add new macro PSP_TMR_ALIGN_SIZE(adev)
to add ASIC specific TMR alignment size support.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2
Wang, Yang(Kevin) would like to recall the message, "[PATCH v2] drm/amdgpu:
change the alignment size of TMR BO to 1M".
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
v2:
add new macro PSP_TMR_ALIGN_SIZE(adev)
to add ASIC specific TMR alignment size support.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2
[AMD Official Use Only - General]
Let’s create a new macro PSP_TMR_ALIGNMENT in case we need to support ASIC
specific TMR alignment in future.
Regards,
Hawking
From: Wang, Yang(Kevin)
Date: Friday, September 9, 2022 at 11:14
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking , Wang, Yang(Kev
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/am
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Friday, September 9, 2022 09:37
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice
Subject: [PATCH v2] drm/amdgpu: Enable full reset when RAS is s
From: "Jiadong.Zhu"
Trigger MCBP according to the priroty of the
software rings and the hw fence signaling
condition.
The muxer records some lastest locations from the
software ring which is used to resubmit packages
in preemption scenarios.
v2: update comment style
Signed-off-by: Jiadong.Zhu
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9.
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
v2: restyle code not to use ternary operator.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/amdg
From: "Jiadong.Zhu"
The software ring is created to support priority
context while there is only one hardware queue
for gfx.
Every software rings has its fence driver and could
be used as an ordinary ring for the gpu_scheduler.
Multiple software rings are binded to a real ring
with the ring muxe
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks
on gfx9.
The software ring could be tested by debugfs_test_ib
case.
v2: set sw_ring 2 to enable software ring by default.
v3: remove the parameter for software ring enablement.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/
Enable full reset for RAS supported configuration on gc v11_0_0.
v2: simplify the code.
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index a26c5723c46
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 47c191411b68a771261be3dc0bd6f68394cef358 Add linux-next specific
files for 20220908
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209042337.fqi69rlv-...@intel.com
https
On 2022-09-07 20:16, Philip Yang wrote:
Prefaulting potentially allocates system memory pages before a
migration. This adds unnecessary overhead. Instead we can skip
unallocated pages in the migration and just point migrate->dst to a
0-initialized VRAM page directly. Then the VRAM page will be
On Thu, Sep 8, 2022 at 1:57 PM Bjorn Helgaas wrote:
>
> On Thu, Sep 08, 2022 at 04:42:38PM +, Lazar, Lijo wrote:
> > I am not sure if ASPM settings can be generalized by PCIE core.
> > Performance vs Power savings when ASPM is enabled will require some
> > additional tuning and that will be de
Please send everything together because otherwise it's not clear why we
need this.
Andrey
On 2022-09-08 11:09, James Zhu wrote:
Yes, it is for NPI design. I will send out patches for review soon.
Thanks!
James
On 2022-09-08 11:05 a.m., Andrey Grodzovsky wrote:
So this is the real need of th
On 2022-09-08 09:17, wangjianli wrote:
Delete the redundant word 'to'.
Signed-off-by: wangjianli
Reviewed-by: Felix Kuehling
I'll apply this to amd-staging-drm-next.
Thanks,
Felix
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 2022-09-08 12:35, Alex Deucher wrote:
On Thu, Sep 8, 2022 at 12:29 PM Felix Kuehling wrote:
On 2022-09-08 11:52, Alex Deucher wrote:
Hi Dave, Daniel,
New stuff for 6.1.
The following changes since commit 085292c3d78015412b752ee1ca4c7725fd2bf2fc:
Revert "drm/amd/amdgpu: add pipe1 hard
On Thu, Sep 08, 2022 at 04:42:38PM +, Lazar, Lijo wrote:
> I am not sure if ASPM settings can be generalized by PCIE core.
> Performance vs Power savings when ASPM is enabled will require some
> additional tuning and that will be device specific.
Can you elaborate on this? In the universe of
[AMD Official Use Only - General]
I am not sure if ASPM settings can be generalized by PCIE core. Performance vs
Power savings when ASPM is enabled will require some additional tuning and that
will be device specific.
In some of the other ASICs, this programming is done in VBIOS/SBIOS firmware.
On Thu, Sep 8, 2022 at 12:29 PM Felix Kuehling wrote:
>
>
> On 2022-09-08 11:52, Alex Deucher wrote:
> > Hi Dave, Daniel,
> >
> > New stuff for 6.1.
> >
> > The following changes since commit 085292c3d78015412b752ee1ca4c7725fd2bf2fc:
> >
> >Revert "drm/amd/amdgpu: add pipe1 hardware support" (
On 2022-09-08 11:52, Alex Deucher wrote:
Hi Dave, Daniel,
New stuff for 6.1.
The following changes since commit 085292c3d78015412b752ee1ca4c7725fd2bf2fc:
Revert "drm/amd/amdgpu: add pipe1 hardware support" (2022-08-16 18:14:31
-0400)
are available in the Git repository at:
https://g
On Thu, Sep 8, 2022 at 12:12 PM Bjorn Helgaas wrote:
>
> [+cc Evan, author of 62f8f5c3bfc2 ("drm/amdgpu: enable ASPM support
> for PCIE 7.4.0/7.6.0")]
>
> On Thu, Sep 08, 2022 at 08:53:44AM +0530, Lijo Lazar wrote:
> > As per PCIE Base Spec r4.0 Section 6.18
> > 'Software must not enable LTR in an
[+cc Evan, author of 62f8f5c3bfc2 ("drm/amdgpu: enable ASPM support
for PCIE 7.4.0/7.6.0")]
On Thu, Sep 08, 2022 at 08:53:44AM +0530, Lijo Lazar wrote:
> As per PCIE Base Spec r4.0 Section 6.18
> 'Software must not enable LTR in an Endpoint unless the Root Complex
> and all intermediate Switches i
Hi Dave, Daniel,
New stuff for 6.1.
The following changes since commit 085292c3d78015412b752ee1ca4c7725fd2bf2fc:
Revert "drm/amd/amdgpu: add pipe1 hardware support" (2022-08-16 18:14:31
-0400)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd
Always keep selected ring sched list in ctx entity.
Later entity->sched_list can always be used to track ring which
is used in this ctx in amdgpu_ctx_fini_entity.
v2: fixed typo
v3. Update comments
Signed-off-by: James Zhu
---
drivers/gpu/drm/scheduler/sched_entity.c | 7 ++-
1 file changed
Yes, it is for NPI design. I will send out patches for review soon.
Thanks!
James
On 2022-09-08 11:05 a.m., Andrey Grodzovsky wrote:
So this is the real need of this patch-set, but this explanation
doesn't appear anywhere in the description.
It's always good to add a short 0 RFC patch which d
So this is the real need of this patch-set, but this explanation doesn't
appear anywhere in the description.
It's always good to add a short 0 RFC patch which describes the
intention of the patchset if the code is
not self explanatory.
And I still don't understand the need - i don't see anythin
To save lines is not the purpose.
Also I want to use entity->sched_list to track ring which is used in
this ctx in amdgpu_ctx_fini_entity
Best Regards!
James
On 2022-09-08 10:38 a.m., Andrey Grodzovsky wrote:
I guess it's an option but i don't really see what's the added value
? You saved
virtual display is enabled unconditionally in SR-IOV, but
without specifying the virtual_display module, the number
of crtcs defaults to 0. Set a single display by default
for SR-IOV if the virtual_display parameter is not set.
Only enable virtual display by default on SR-IOV on asics
which actual
Move it into the DCE code for each generation. This avoids
confusion with the different display paths.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 35 +
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c |
There are several places where we don't want to check
if a particular asic could support DC, but rather, if
DC is enabled. Set a flag if DC is enabled and check
for that rather than if a device supports DC or not.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h |
amdgpu_device_asic_has_dc_support() just checks the asic itself.
amdgpu_device_has_dc_support() is a runtime check which not
only checks the asic, but also other things in the driver
like whether virtual display is enabled. We want the latter
here.
Signed-off-by: Alex Deucher
---
drivers/gpu/dr
I guess it's an option but i don't really see what's the added value ?
You saved a few lines in this patch
but added a few lines in another. In total seems to me no to much
difference ?
Andrey
On 2022-09-08 10:17, James Zhu wrote:
Hi Andrey
Basically this entire patch set are derived from p
Ping on this series?
Alex
On Tue, Jul 19, 2022 at 2:35 PM Alex Deucher wrote:
>
> amdgpu_device_asic_has_dc_support() just checks the asic itself.
> amdgpu_device_has_dc_support() is a runtime check which not
> only checks the asic, but also other things in the driver
> like whether virtual disp
On Thu, Sep 8, 2022 at 1:11 AM Lazar, Lijo wrote:
>
>
>
> On 9/8/2022 9:38 AM, Alex Deucher wrote:
> > Common is mainly golden register setting and HDP register
> > remapping, it shouldn't allocate any GPU memory. Make sure
> > common happens before gmc so that the HDP registers are
> > remapped
Hi Andrey
Basically this entire patch set are derived from patch [3/4]:
entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
I think no special reason to treat single and multiple schedule list here.
Best Regards!
James
On 2022-09-08 10:08 a.m., Andrey Grodzovsky wrote:
What's the
On Thu, Sep 8, 2022 at 10:08 AM Deucher, Alexander
wrote:
>
> [Public]
>
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Bjorn Helgaas
> > Sent: Thursday, August 25, 2022 2:02 PM
> > To: Lazar, Lijo
> > Cc: Greg Kroah-Hartman ; Kuehling, Felix
> > ; amd-gfx@lists.freedesktop.or
What's the reason for this entire patch set ?
Andrey
On 2022-09-07 16:57, James Zhu wrote:
drm_sched_pick_best returns struct drm_gpu_scheduler ** instead of
struct drm_gpu_scheduler *
Signed-off-by: James Zhu
---
include/drm/gpu_scheduler.h | 2 +-
1 file changed, 1 insertion(+), 1 deleti
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Bjorn Helgaas
> Sent: Thursday, August 25, 2022 2:02 PM
> To: Lazar, Lijo
> Cc: Greg Kroah-Hartman ; Kuehling, Felix
> ; amd-gfx@lists.freedesktop.org;
> tseew...@gmail.com; Deucher, Alexander
> ; s...@denx.de; Koenig, Christia
Hi Christian
I need use entity->sched_list to track ring (ring = container_of(sched,
struct amdgpu_ring, sched))
during amdgpu_ctx_fini_entity.
I think change here to keep selected ring sched list in
entity->sched_list won't change the original logic too much.
Best Regards!
James
On 202
Delete the redundant word 'in'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index bdb6bac8dd97..c9
Delete the redundant word 'to'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 24b414cff3ec..cd5f8b219bf9 100644
--- a/dri
On Tue, Sep 6, 2022 at 3:58 PM Hamza Mahfooz wrote:
>
> Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
> drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
> struct.
>
> Signed-off-by: Hamza Mahfooz
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu
On 9/8/2022 11:34 AM, Christian König wrote:
Am 07.09.22 um 19:00 schrieb Daniel Vetter:
[SNIP]
I'm a bit confused why the bloat here ...
Drivers do have specialized implementations of the backend, e.g.
VMWGFX have
his handle backend, amdgpu the VRAM backend with special placements,
i915 i
Am 07.09.22 um 20:11 schrieb Pavle Kotarac:
From: Taimur Hassan
[Why & How]
When calculating cursor size for MALL allocation, the cursor width should
be the actual width rounded up to 64 alignment. Additionally, the bit
depth should vary depending on color format.
Reviewed-by: Alvin Lee
Ac
[AMD Official Use Only - General]
Good point, thanks for the review. I will send a new one.
Thanks,
Candice
-Original Message-
From: Kuehling, Felix
Sent: Thursday, September 8, 2022 11:54 AM
To: Li, Candice ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Enable full
The variable i is already declared as uint32_t in the same function.
This fixes the following error, when compiling this code on older kernel:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c: In function
'dcn32_full_validate_bw_helper':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/
PF will do page retirement, reset VF and inform VF to reserve RAS bad pages.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 18 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c| 6 ++
drivers/gpu/drm/amd/am
V3:
[Why]:
Since ASICs using smu v13_0_2 have called smu
.suspend before calling amdgpu_pm_sysfs_fini,
pm.dpm_enabled was already set to 0 when smu
.suspend was called. This makes it impossible
to delete all pm sys nodes.
[How]:
Since all functions in amdgpu_pm_sysfs_fini
have their own condit
V3:
Fixed psp fence and memory issues for the asic
using smu v13_0_2 when removing amdgpu device.
[Why]:
1. psp_suspend->psp_free_shared_bufs->
psp_ta_free_shared_buf->
amdgpu_bo_free_kernel->
...->amdgpu_bo_release_notify->
amdgpu_fill_buffer
Adjust removal control flow for smu v13_0_2:
During amdgpu uninstallation, when removing the first
device, the kernel needs to first send a mode1reset message
to all gpu devices. Otherwise, smu initialization will fail
the next time amdgpu is installed.
V2:
1. Update commit comments.
2. Remove
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